M48Z2M1

M48Z2M1Y

16 Mb (2Mb x 8) ZEROPOWER

January 1998

1/12

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

INTEGRATED LOW POWER SRAM,

POWER-FAIL CONTROL CIRCUIT and

BATTERIES

CONVENTIONAL SRAM OPERATION;

UNLIMITED WRITE CYCLES

10 YEARS of DATA RETENTION in the

ABSENCE of POWER

AUTOMATIC POWER-FAIL CHIP DESELECT

and WRITE PROTECTION

WRITE PROTECT VOLTAGES

– M48Z2M1: 4.5V

– M48Z2M1Y: 4.2V

BATTERIES ARE INTERNALLY ISOLATED

UNTIL POWER IS APPLIED

PIN and FUNCTION COMPATIBLE with

JEDEC STANDARD 2Mb x 8 SRAMs

DESCRIPTION

non-volatile 16,777,216 bit Static RAM organized

as 2,097,152 words by 8 bits. The device combines

two internal lithium batteries, CMOS SRAMs and a

control circuit in a plastic 36 pin DIP long Module.

The ZEROPOWER RAM replaces industry stand-

ard SRAMs. It provides the nonvolatility of PROMs

without any requirement for special write timing or

limitations on the number of writes that can be

performed.

AI02048

21

A0-A20

W

DQ0-DQ7

VCC

M48Z2M1

M48Z2M1Y

G

VSS

8

E

Figure 1. Logic Diagram

A0-A20

Address Inputs

DQ0-DQ7

Data Inputs / Outputs

E

Chip Enable

G

Output Enable

W

Write Enable

Supply Voltage

Ground

Table 1. Signal Names

36

1

PMLDIP36 (PL)

Module