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M48Z2M1 数据表(PDF) 2 Page - STMicroelectronics |
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M48Z2M1 数据表(HTML) 2 Page - STMicroelectronics |
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2 / 12 page ![]() Symbol Parameter Value Unit TA Ambient Operating Temperature 0 to 70 °C TSTG Storage Temperature (VCC Off) –40 to 85 °C TBIAS Temperature Under Bias –40 to 85 °C TSLD (2) Lead Soldering Temperature for 10 seconds 260 °C VIO Input or Output Voltages –0.3 to 7 V VCC Supply Voltage –0.3 to 7 V Notes: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect reliability. 2. Soldering temperature not to exceed 260 °C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds). CAUTION: Negative undershoots below –0.3 volts are not allowed on any pin while in the Battery Back-up mode. Table 2. Absolute Maximum Ratings (1) Mode VCC E G W DQ0-DQ7 Power Deselect 4.75V to 5.5V or 4.5V to 5.5V VIH X X High Z Standby Write VIL XVIL DIN Active Read VIL VIL VIH DOUT Active Read VIL VIH VIH High Z Active Deselect VSO to VPFD (min) X X X High Z CMOS Standby Deselect ≤ VSO X X X High Z Battery Back-up Mode Notes: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage. Table 3. Operating Modes VSS VCC AI02049 M48Z2M1 M48Z2M1Y 10 1 2 5 6 7 8 9 11 12 13 16 17 18 30 29 26 25 24 23 22 21 20 19 3 4 28 27 32 31 14 15 34 33 36 35 A1 A0 DQ0 A7 A4 A3 A2 A6 A5 A13 A10 A8 A9 DQ7 A15 A11 G E DQ5 DQ1 DQ2 DQ3 DQ4 DQ6 A16 A18 A12 A14 W A17 A20 NC NC A19 Figure 2. DIP Pin Connections The M48Z2M1/2M1Y has its own Power-fail Detect Circuit. The control circuitry constantly monitors the single 5V supply for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system op- erations brought on by low VCC. As VCC falls below approximately 3V, the control circuitry connects the batteries which sustain data until valid power re- turns. READ MODE The M48Z2M1/2M1Y is in the Read Mode when- ever W (Write Enable) is high and E (Chip Enable) is low. The device architecture allows ripple- through access of data from eight of 16,777,216 locations in the static storage array. Thus, the unique address specified by the 21 Address Inputs defines which one of the 2,097,152 bytes of data is to be accessed. Valid data will be available at the Data I/O pins within Address Access time (tAVQV) after the last address input signal is stable, provid- ing that the E (Chip Enable) and G (Output Enable) access times are also satisfied. If the E and G access times are not met, valid data will be avail- DESCRIPTION (cont’d) Warning: NC = Not Connected. 2/12 M48Z2M1, M48Z2M1Y |
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