able after the later of Chip Enable Access time

state of the eight three-state Data I/O signals is

controlled by E and G. If the outputs are activated

puts are changed while E and G remain low, output

data will remain valid for Output Data Hold time

dress Access.

WRITE MODE

The M48Z2M1/2M1Y is in the Write Mode when-

ever W and E are active. The start of a write is

referenced from the latter occurring falling edge of

W or E. A write is terminated by the earlier rising

edge of W or E.

The addresses must be held valid throughout the

another read or write cycle. Data-in must be valid

high during write cycles to avoid bus contention;

although, if the output bus has been activated by a

low on E and G, a low on W will disable the outputs

AI01030

5V

OUT

CL = 100pF or 5pF

CL includes JIG capacitance

1.9k

Ω

DEVICE

UNDER

TEST

1k

Ω

Figure 4. AC Testing Load Circuit

Input Rise and Fall Times

≤ 5ns

Input Pulse Voltages

0 to 3V

Input and Output Timing Ref. Voltages

1.5V

Note that Output Hi-Z is defined as the point where data is no

longer driven.

Table 4. AC Measurement Conditions

AI02050

INTERNAL

BATTERIES

E

VCC

VSS

VOLTAGE SENSE

AND

SWITCHING

CIRCUITRY

2048K x 8

SRAM ARRAY

A0-A20

DQ0-DQ7

W

G

POWER

E

Figure 3. Block Diagram

3/12

M48Z2M1, M48Z2M1Y