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M50LPW040K 数据表(PDF) 2 Page - STMicroelectronics

部件名 M50LPW040K
功能描述  4 Mbit 512Kb x8, Uniform Block 3V Supply Low Pin Count Flash Memory
PDF  36 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

M50LPW040K 数据表(HTML) 2 Page - STMicroelectronics

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M50LPW040
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Figure 2. Logic Diagram (A/A Mux Interface)
AI05436
11
RC
DQ0-DQ7
VCC
M50LPW040
IC
VSS
8
G
W
RB
RP
A0-A10
VPP
DESCRIPTION
The M50LPW040 is a 4 Mbit (512Kb x8) non-
volatile memory that can be read, erased and
reprogrammed.
These
operations
can
be
performed using a single low voltage (3.0 to 3.6V)
supply. For fast programming and fast erasing in
production lines an optional 12V power supply can
be used to reduce the programming and the
erasing times.
The memory is divided into blocks that can be
erased independently so it is possible to preserve
valid data while old data is erased. Blocks can be
protected
individually
to
prevent
accidental
Program or Erase commands from modifying the
memory. Program and Erase commands are
written to the Command Interface of the memory.
An on-chip Program/Erase Controller simplifies
the process of programming or erasing the
memory by taking care of all of the special
operations that are required to update the memory
contents. The end of a program or erase operation
can
be
detected
and
any
error
conditions
identified. The command set required to control
the memory is consistent with JEDEC standards.
Two different bus interfaces are supported by the
memory. The primary interface is the Low Pin
Count (or LPC) Standard Interface. This has been
designed to remove the need for the ISA bus in
Figure 3. TSOP Connections
AI05437
A1
A0
DQ0
A7
A4
A3
A2
A6
A5
A9
A8
W
VSS
VCC
DQ7
G
RB
DQ5
DQ1
DQ2
DQ3
DQ4
DQ6
ID1
LAD1
LAD2
GPI3
TBL
ID2
GPI0
WP
NC
VCC
NC
IC (VIL)
RFU
GPI4
NC
VSS
LFRAME
RFU
LAD3
VSS
VCC
RFU
RFU
NC
CLK
RP
NC
VPP
VCC
NC
M50LPW040
10
1
11
20
21
30
31
40
RFU
NC
INIT
NC
RFU
GPI2
LAD0
GPI1
ID0
VSS
NC
NC
NC
IC (VIH)
NC
NC
NC
NC
RC
RP
VPP
VCC
NC
A10
VSS
VSS
VCC



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