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PRELIMINARY DATA

March 2002

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

M50LPW040

4 Mbit (512Kb x8, Uniform Block)

3V Supply Low Pin Count Flash Memory

s

SUPPLY VOLTAGE

Read Operations

(optional)

s

TWO INTERFACES

– Low Pin Count (LPC) Standard Interface for

embedded operation with PC Chipsets.

– Address/Address Multiplexed (A/A Mux) In-

terface for programming equipment compati-

bility.

s

LPC HARDWARE INTERFACE MODE

– 5 Signal Communication Interface supporting

Read and Write Operations

– Hardware Write Protect Pins for Block Pro-

tection

– Register Based Read and Write Protection

– 5 Additional General Purpose Inputs for plat-

form design flexibility

– Synchronized with 33 MHz PCI clock

s

PROGRAMMING TIME

– 10µs typical

– Quadruple Byte Programming Option

s

8 UNIFORM 64 Kbyte MEMORY BLOCKS

s

PROGRAM/ERASE CONTROLLER

– Embedded Byte Program and Block/Chip

Erase algorithms

– Status Register Bits

s

PROGRAM and ERASE SUSPEND

– Read other Blocks during Program/Erase

Suspend

– Program other Blocks during Erase Suspend

s

FOR USE in PC BIOS APPLICATIONS

s

ELECTRONIC SIGNATURE

– Manufacturer Code: 20h

– Device Code: 26h

Figure 1. Logic Diagram (LPC Interface)

AI05435

3

LFRAME

LAD0-

LAD3

VCC

M50LPW040

CLK

VSS

4

IC

RP

TBL

5

INIT

WP

ID0-ID2

GPI0-

GPI4

VPP

TSOP40 (N)

10 x 20mm

PLCC32 (K)