M50LPW040K datasheet(4/36 Pages) STMICROELECTRONICS

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M50LPW040

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Low Pin Count (LPC) Signal Descriptions

For the Low Pin Count (LPC) Interface see Figure

1, Logic Diagram, and Table 1, Signal Names.

Input/Output Communications (LAD0-LAD3). All

Input and Output Communication with the memory

take place on these pins. Addresses and Data for

Bus Read and Bus Write operations are encoded

on these pins.

Input Communication Frame (LFRAME). The

Input Communication Frame (LFRAME) signals

the start of a bus operation. When Input Commu-

nication Frame is Low, VIL, on the rising edge of

the Clock a new bus operation is initiated. If Input

Communication Frame is Low, VIL, during a bus

operation then the operation is aborted. When In-

put Communication Frame is High, VIH, the cur-

rent bus operation is proceeding or the bus is idle.

Identification Inputs (ID0-ID2). The Identification

Inputs (ID0-ID2) allow to address up to 8

memories on a bus. The value on addresses A19-

A21 is compared to the hardware strapping on the

ID0-ID2 pins to select which memory is being

addressed. For an address bit to be ‘1’ the

correspondent ID pin can be left floating or driven

Low, VIL; an internal pull-down resistor is included

with a value of RIL. For an address bit to be ‘0’ the

correspondent ID pin must be driven High, VIH;

there will be a leakage current of ILI2 through each

pin when pulled to VIH; see Table 20.

By convention the boot memory must have ID0-

ID2 pins left floating or driven Low, VIL and a ‘111’

value on A19-A21 and all additional memories

take sequential ID0-ID2 configuration, as shown in

Table 2.

General Purpose Inputs (GPI0-GPI4). The Gener-

al Purpose Inputs can be used as digital inputs for

the CPU to read. The General Purpose Input Reg-

ister holds the values on these pins. The pins must

have stable data from before the start of the cycle

that reads the General Purpose Input Register un-

til after the cycle is complete. These pins must not

be left to float, they should be driven Low, VIL, or

High, VIH.

Interface Configuration (IC). The Interface Con-

figuration input selects whether the Low Pin Count

(LPC) or the Address/Address Multiplexed (A/A

Mux) Interface is used. The chosen interface must

be selected before power-up or during a Reset

and, thereafter, cannot be changed. The state of

the Interface Configuration, IC, should not be

changed during operation.

To select the Low Pin Count (LPC) Interface the

Interface Configuration pin should be left to float or

driven Low, VIL; to select the Address/Address

Multiplexed (A/A Mux) Interface the pin should be

driven High, VIH. An internal pull-down resistor is

included with a value of RIL; there will be a leakage

current of ILI2 through each pin when pulled to VIH;

see Table 20.

Interface Reset (RP). The Interface Reset (RP)

input is used to reset the memory. When Interface

Reset (RP) is set Low, VIL, the memory is in Reset

mode: the outputs are put to high impedance and

the current consumption is minimized. When RP is

set High, VIH, the memory is in normal operation.

After exiting Reset mode, the memory enters

Read mode.

CPU Reset (INIT). The CPU Reset, INIT, pin is

used to Reset the memory when the CPU is reset.

It behaves identically to Interface Reset, RP, and

the internal Reset line is the logical OR (electrical

AND) of RP and INIT.

Clock (CLK). The Clock, CLK, input is used to

clock the signals in and out of the Input/Output

Communication Pins, LAD0-LAD3. The Clock

conforms to the PCI specification.

Table 2. Memory Identification Input Configuration

Memory Number

ID2

ID1

ID0

A21

A20

A19

1 (Boot)

VIL or floating

VIH

VIL or floating

VIH

VIL or floating

VIH

VIL or floating

VIH

VIL or floating

VIH

VIL or floating

VIH

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