8 Detailed Description

8.1 Overview

Most SAR ADCs, and a few delta-sigma ADCs, switch binary-weighted capacitors onto the REF pin during

the conversion process. The magnitude of the capacitance switched onto the REF pin during each conversion

depends on the input signal to the ADC. If a voltage reference is directly connected to the REF pin of these

ADCs, the reference voltage droops because of the dynamic input signal dependent load of the binary-weighted

capacitors. Because the reference voltage droop now has input signal dependance, significant degradation in

THD and linearity for the system occurs.

In order to support this dynamic load and preserve the ADC linearity, distortion and noise performance, the

output of the voltage reference must be buffered with a low-output impedance (high-bandwidth) buffer. The

REF60xx family of voltage references have an integrated low output impedance buffer that enables the user to

directly drive the REF pin of a SAR ADC, while preserving ADC linearity and distortion. In addition, the total

noise in the full bandwidth of the REF60xx is extremely low, thus preserving the noise performance of the ADC.

Voltage-Reference Impact on Total Harmonic Distortion (SLYY097) correlates the effect of reference settling to

ADC distortion, and how the REF60xx achieves lowest distortion with minimal components and lowest power

consumption.

The output voltage of the REF60xx does not droop below 1LSB (18-bit), even during the first conversion while

driving the REF pin of the ADS8881. This feature is useful in burst-mode, event-triggered, equivalent-time

sampling, and variable-sampling-rate data-acquisition systems. Section 8.2 shows a simplified schematic of the

REF60xx.

8.2 Functional Block Diagram

Bandgap

Voltage

Reference

RFILT

Buffer

+

VIN

OUT_S

OUT_F

FILT

VIN

GND_S

GND_F

SS

EN

www.ti.com

REF60

SBOS708C – MAY 2016 – REVISED APRIL 2026

Copyright © 2026 Texas Instruments Incorporated

Submit Document Feedback

19

Product Folder Links: REF60