APM32F103CBT6-R datasheet(38/78 Pages) GEEHY

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P a g e 37

5.7.2

Power consumption in operation mode

Table25 Power consumption of data processing code running in Flash in operation mode

Parameter

Condition

fHCLK

Typical value (1)

Maximum value (1)

TA=25℃，VDD=3.3V

TA=105℃，VDD=3.6V

IDDA

(μA)

IDD (mA）

IDDA

(μA)

IDD (mA)

Power

consumption in

operation

mode

External clock (2), enabling all

peripherals

96MHz

206.26

30.47

247.93

35.64

72MHz

131.44

25.26

155.42

25.36

48MHz

97.02

17.99

119.82

20.82

36MHz

73.59

13.79

95.39

15.68

24MHz

54.06

9.89

74.46

11.54

16MHz

42.85

6.82

62.58

8.14

8MHz

2.66

3.64

5.8

4.61

External clock (2), disabling all

peripherals

96MHz

205.98

20.02

242.41

22.74

72MHz

130.91

14.99

153.66

16.74

48MHz

96.92

12.67

114.87

14.33

36MHz

73.54

9.69

89.39

11.05

24MHz

54.06

7.21

68.85

8.45

16MHz

42.85

5.06

57.38

6.11

8MHz

2.66

2.75

5.68

3.63

The data are obtained from a comprehensive evaluation and are not tested in production.

The external clock is 8MHz. When fHCLK > 8MHz, the PLL is enabled.

Table26 Power consumption of data processing code running in RAM in operation mode

Parameter

Condition

fHCLK

Typical value (1)

Maximum value (1)

TA=25℃，VDD=3.3V

TA=105℃，VDD=3.6V

IDDA

(μA)

IDD (mA）

IDDA

(μA)

IDD (mA)

Power

consumption in

operation

mode

External clock (2), enabling all

peripherals

96MHz

206.68

29.97

250.48

59.83

72MHz

131.66

20.61

161.87

24.58

48MHz

97.59

15.71

122.43

67.9

36MHz

74.15

11.95

96.93

14.16

24MHz

54.80

8.36

72.68

9.93

16MHz

43.44

5.68

60.53

6.97

8MHz

2.63

3.07

3.96

External clock (2), disabling all

peripherals

96MHz

183.81

22.82

245.72

27.37

72MHz

117.42

17.14

159.32

18.66

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