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APM32F103CBT6-R 数据表(PDF) 46 Page - Geehy Semiconductor Co., Ltd. |
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APM32F103CBT6-R 数据表(HTML) 46 Page - Geehy Semiconductor Co., Ltd. |
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46 / 78 page ![]() w w w. g e e h y. c o m P a g e 45 5.11 Communication peripherals 5.11.1 I2C peripheral characteristics Table37 I2C Interface Characteristics (TA=25 ℃, V DD=3.3V) Symbol Parameter Standard I2C (1) Standard I2C (1) (2) Unit Minimum value Maximu m value Minimum value Maximu m value tw(SCLL) SCL clock low time 4.7 - 1.3 - μs tw(SCLH) SCL clock high time 4.0 - 0.6 - tsu(SDA) SDA setup time 250 - 100 - ns th(SDA) SDA data hold time 0(3) - 0(4) 9003) tr(SDA) tr(SCL) SDA and SCL rise time - 1000 20+0.1Cb 300 tf(SDA) tf(SCL) SDA and SCL fall time - 300 - 300 th(STA) Start condition hold time 4.0 - 0.6 - μs tsu(STA) Setup time of repeated start condition 4.7 - 0.6 - tsu(STO) Setup time of stop condition 4.0 - 0.6 - μs tw(STO:STA) Time from stop condition to start condition (the bus is idle) 10.86 - 3.85 - μs 1. Guaranteed by design and not tested in production. 2. To achieve the maximum frequency of I2C in standard mode, fPCLK1 must be greater than 2MHz. To achieve maximum frequency of I2C in fast mode, fPCLK1 must be greater than 4MHz. 3. If you do not want to prolong the low-level time of SCL signal, the maximum hold time of the start condition must be met. 4. In order to cross the undefined area of the falling edge of SCL, the SDA signal must have a hold time of at least 300ns in the MCU. |
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