M58LW064 datasheet(23/53 Pages) STMICROELECTRONICS

23 / 53 page

23/53

M58LW064A, M58LW064B

Set Burst Configuration Register (SBCR).

This instruction uses two command cycles. The

Burst Configuration Setup command 60h is written

with the address corresponding to the Set Burst

Configuration Register content. Then in the sec-

ond write cycle the address bus A2-A17 specifies

the BCR, Burst Configuration Register, informa-

tion and the command 03h. The burst length, type,

latency, synchronous/asynchronous read mode

and clock edge active configuration are defined in

that operation. After the command 03h the device

will default in the Read array mode.

Status Register Bits. The P/E.C. status is indi-

cated during execution with a Ready/Busy output

available on DQ7. Any read attempt during Pro-

gram or Erase command execution will automati-

cally update the Status Register bits. The P/E.C.

automatically sets bits DQ1, DQ2, DQ4, DQ5,

DQ6 and DQ7. The bit DQ0 is reserved for future

use and should be masked. It is not necessary to

specify an address when the Status Register bits

are read. The Status Register is a static memory

a power-down operation.

POWER SUPPLY

Power Down. The memory provides Reset/Pow-

er-down control using the input RP. When Reset/

Power-down RP is pulled to VIL the supply current

drops to typically less than 1

µA, the memory is de-

selected and the outputs are at high impedance. If

RP is pulled to VIL during a Program or Erase op-

eration, this operation is aborted after a latency

time of tPLRH and the memory content is no longer

valid.

RESET, POWER-DOWN AND POWER-UP

See Fig 16.

The device is reset if the Reset/Power-down RP

input is pulled to VIL for longer than tPLPH. If the

device was in a Read mode then it will recover

from reset after a time of tPHQV to give valid data

output. If the device was executing an Erase or

Program operation, with the P/E.C. active, the op-

eration will abort in a time of tPLRH maximum. The

device will be ready to accept new write com-

mends after a time of tPHWL or tPHEL.

The supply voltages VDD and VDDQ must be high

a time tVDHEL or tVDHWL before a read or write cy-

cle. At first power up Reset/Power-down should be

held Low for a time of tVDHPH after VDD and VDDQ

are high. The device will be ready to accept its first

read or write commands after a time of tPUR or

tPUW.

COMMON FLASH INTERFACE - CFI

The introduction to the JEDEC CFI specification

Rel. 1.2 quotes, ”The Common Flash Interface

(CFI) specification outlines a device and host sys-

tem software interrogation handshake which al-

lows specific software algorithms to be used for

entire families of devices. This allows device-inde-

pendent, JEDEC, ID independent and forward-

and backward-compatible software support for the

specified flash device families. It allows flash ven-

dors to standardize their existing interfaces for

long-term compatibility.”

The CFI Query instruction RCFI describes how the

device enters the CFI Query mode which enables

information to be read from the Flash memory. CFI

allows a system software to query the flash device

to determine various electrical and timing parame-

ters, density information and functions supported

by the device. CFI allows the system to easily in-

terface to the flash memory, to learn about its fea-

tures and parameters, enabling the software to

upgrade itself when necessary.

Query Structure Overview

The flash memory displays the CFI data structure

when the CFI Query Instruction RCFI is issued. A

list of the main subsections is detailed in Tables 15

to 19.

M58LW064 数据表(PDF) 23 Page - STMicroelectronics

M58LW064 数据表(HTML) 23 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

数据表下载