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RA4M3 数据表(PDF) 53 Page - Renesas Technology Corp |
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RA4M3 数据表(HTML) 53 Page - Renesas Technology Corp |
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53 / 98 page  2.3.9 SPI Timing Table 2.27 SPI timing Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register. Parameter Symbol Min Max Unit Test conditions SPI RSPCK clock cycle Master tSPcyc 2 4096 tPcyc Figure 2.34 Slave 4 4096 RSPCK clock high pulse width Master tSPCKWH (tSPcyc – tSPCKr – tSPCKf) / 2 – 3 — ns Slave 0.4 0.6 tSPcyc RSPCK clock low pulse width Master tSPCKWL (tSPcyc – tSPCKr – tSPCKf) / 2 – 3 — ns Slave 0.4 0.6 tSPcyc RSPCK clock rise and fall time Master tSPCKr, tSPCKf — 5 ns Slave — 1 µs Data input setup time Master tSU 4 — ns Figure 2.35 to Figure 2.40 Slave 5 — Data input hold time Master (PCLKA division ratio set to 1/2) tHF 0 — ns Master (PCLKA division ratio set to a value other than 1/2) tH tPcyc — Slave tH 20 — SSL setup time Master tLEAD N × tSPcyc - 10*1 N × tSPcyc + 100*1 ns Slave 4 × tPcyc — ns SSL hold time Master tLAG N × tSPcyc - 10*2 N × tSPcyc + 100*2 ns Slave 4 × tPcyc — ns Data output delay Master tOD1 — 6.3 ns tOD2 — 6.3 Slave tOD — 20 Data output hold time Master tOH 0 — ns Slave 0 — Successive transmission delay Master tTD tSPcyc + 2 × tPcyc 8 × tSPcyc + 2 × tPcyc ns Slave 4 × tPcyc MOSI and MISO rise and fall time Output tDr, tDf — 5 ns Input — 1 µs SSL rise and fall time Output tSSLr, tSSLf — 5 ns Input — 1 µs Slave access time tSA — 25 ns Figure 2.39 and Figure 2.40 Slave output release time tREL — 25 Note: tPcyc: PCLKA cycle. RA4M3 Datasheet 2. Electrical Characteristics R01DS0368EJ0150 Rev.1.50 Apr 25, 2025 Page 53 of 98 |
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