RA4M3 datasheet(64/98 Pages) RENESAS

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tSR

tHR

tDTR

SSIBCK0

(Input or Output)

SSILRCK0/SSIFS0 (input),

SSIRXD0,

SSIDATA0 (input)

SSILRCK0/SSIFS0 (output),

SSITXD0,

SSIDATA0 (output)

Figure 2.47

SSIE data transmit and receive timing when SSICR.BCKP = 1

tDTRW

SSILRCK0/SSIFS0 (input)

SSITXD0,

SSIDATA0 (output)

MSB bit output delay after SSILRCK0/SSIFS0 change for slave

transmitter when DEL = 1, SDTA = 0 or DEL = 1, SDTA = 1, SWL[2:0] = DWL[2:0] in SSICR.

Figure 2.48

SSIE data output delay after SSILRCK0/SSIFS0 change

2.3.13

SD/MMC Host Interface Timing

Table 2.32

SD/MMC Host Interface signal timing (n = 0, m = 0 to 7)

Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Clock duty ratio is 50%.

Parameter

Symbol

Min

Max

Unit

Test conditions

SDnCLK clock cycle

TSDCYC

—

Figure 2.49

SDnCLK clock high pulse width

TSDWH

6.5

—

SDnCLK clock low pulse width

TSDWL

6.5

—

SDnCLK clock rise time

TSDLH

—

SDnCLK clock fall time

TSDHL

—

SDnCMD/SDnDATm output data delay

TSDODLY

–7

SDnCMD/SDnDATm input data setup

TSDIS

4.5

—

SDnCMD/SDnDATm input data hold

TSDIH

1.5

—

RA4M3 Datasheet

2. Electrical Characteristics

R01DS0368EJ0150 Rev.1.50

Apr 25, 2025

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