AS3953 datasheet(46/71 Pages) AMSOSRAM

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[v1-05] 2019-Feb-15

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AS3953A − Detailed Description

FIFO underflow is set when data was read from empty FIFO. In

case this bit is set during reception the external controller read

more data than was actually received. During transmission this

means that controller has failed to provide the quantity of data

defined in number of transmitted bytes registers on time.

ISO 14443A Frame Data in FIFO

Data in ISO 14443A frames is organized in bytes; each byte is

terminated by parity bit. Data bits in a byte are numbered from

b1 to b8 where b1 is LSB bit, LSB is sent first.

Data sent over SPI is also organized in bytes, bits in a byte are

marked D0 to D7, where D0 is LSB bit, MSB is sent first.

During receive the framing engine checks the parity bit and

removes it from data frame, only the data bytes are put in FIFO.

During transmission the process is inversed, only the data bytes

are put in FIFO, while the framing engine adds the parity bits.

The ISO 14443A data bits b1 to b8 are mapped to FIFO data bits

D0 to D7, which means that the order of receiving/transmitting

bits in a byte is inversed (the ISO 14443A bytes are sent LSB first

while the SPI bytes are sent MSB first).

The only exceptions to this rule are the Rx and Tx bit stream

modes. In these modes the meaning of byte is lost. In order to

simplify processing the order of bits is the same on ISO 14443A

and FIFO side.

This means that during reception with bit rxbs set the first

received bit is also the first bit read out of FIFO. In case the last

FIFO byte is not complete the bits which are not part of received

data are padded with ‘0’.

The same stands for transmission with bit txbs set: the first bit

written in FIFO is also the first bit sent.

Direct Commands

Figure 52:

List of Direct Commands

Command Byte

Value [hex]

Command

Comments

C2, C3

Set Default

Puts the AS3953A in default state

C4, C5

Clear

Stops all activities and clears FIFO

Transmit

Starts a transmit sequence

Go2halt

Puts PICC logic in HALT state

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