AS3953 datasheet(22/71 Pages) AMSOSRAM

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[v1-05] 2019-Feb-15

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AS3953A − Detailed Description

TA(1): This codes the bit rate capability of PICC. Supported

higher bit rates of AS3953A are 212, 424 and 848 kbit/s.

However in specific applications, it is advised to report lower

capability to PCD (for example, due to the usage of slow

controller or low power application). Due to this reason the

TA(1) response is configurable using configuration bits.

Figure 22:

TA(1) Byte Coding

Bit b8 set to ‘0’ codes possibility of having different data rates

for each direction.

TB(1): The interface byte TB(1) conveys information to define

the frame waiting time and the start-up frame guard time. The

interface byte TB(1) consists of two parts:

• The most significant half-byte b8 to b5 is called FWI and

codes frame waiting time (FWT).

• The least significant half byte b4 to b1 is called SFGI and

codes a multiplier value used to define the SFGT. The SFGT

defines a specific guard time needed by the PICC before

it is ready to receive the next frame after it has sent the

ATS. SFGI is coded in the range from 0 to 14. The value of

‘0’ indicates ‘No SFGT needed’.

The SFGT bits are fixed to default value which is 0x0, while the

FWI bits are defined by configuration bits fwi<3:0>. Figure

below defines the coding of the TB(1) byte.

Figure 23:

TB(1) Byte Coding

MSB

LSB

Description

dr_sdr

dr_

picc_8

dr_

picc_4

dr_

picc_2

dr_

pcd_8

dr_

pcd_4

dr_

pcd_2

Coding of ATS byte TA(1)

DS (PICC to PCD)

DR (PCD to PICC)

MSB

LSB

Description

fwi<3>

fwi<2>

fwi<1>

fwi<0>

Coding of ATS byte TB(1)

FWI

SFGI

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