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R5F10DMDCLFB 数据表(PDF) 117 Page - Renesas Technology Corp |
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R5F10DMDCLFB 数据表(HTML) 117 Page - Renesas Technology Corp |
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117 / 139 page  RL78/D1A 4. ELECTRICAL SPECIFICATIONS (L GRADE PRODUCT) R01DS0463EJ0120 Rev. 1.20 Page 117 of 135 Mar 31, 2026 4.5.4 Serial interface: CSI operation <Master mode> TA = -40 to +105 °C 2.7 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V Items Symbols Conditions Min. Max. Unit SCK cycle time tKCY1 4.0 V ≤VDD 167 tKCY1 ≥4/fCLKNote ns VDD<4.0 V 250 ns SCK high/low level width tKH1 tKL1 4.0 V ≤VDD tKCY1/2-12 ns VDD<4.0 V tKCY1/2-18 ns SI set up time tSIK1 4.0 V ≤VDD 44 ns VDD<4.0 V 55 Ns SI hold time tKSI1 19 ns SO output delay time tKSO1 C = 30 pF 25 ns Note When CSI transfer is operated by DMA, it is necessary to concider DMA response time to decide cycle time. Caution Different voltage between EVDD and VDD is allowed only when LCDM register is initial value. <Slave mode> TA = -40 to +105 °C 2.7 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V Items Symbols Conditions Min. Max. Unit SCK cycle time tKCY2 4.0 V ≤EVDD 20 MHz<fMCK 8/fMCK ns fMCK ≤20 MHz 6/fMCK ns EVDD<4.0 V 16 MHz<fMCK 8/fMCK ns fMCK ≤16 MHz 6/fMCK ns SCK high/low level width tKH2 tKL2 tKCY2/2 ns SI set up time tSIK2 2.7 V ≤EVDD 1/fMCK+40 ns SI hold time tKSI2 1/fMCK+62 ns SO output delay time tKSO2 C = 30pF 4.0 V ≤EVDD 2/fMCK+44 ns EVDD<4.0 V 2/fMCK+57 ns Note When CSI transfer is operated by DMA, it is necessary to concider DMA response time to decide cycle time. Caution Different voltage between EVDD and VDD is allowed only when LCDM register is initial value. Figure 4-6. CSI mode connection diagram D1A SCK User's device SCK SO SI SO SI <master> <slave> D1A SCK User's device SCK SO SI SO SI <R> <R> <R> <R> <R> <R> |
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