R5F566TFCDFB datasheet(16/151 Pages) RENESAS

16 / 151 page

R01DS0315EJ0130 Rev.1.30

Page 16 of 151

Oct 06, 2023

RX66T Group

1. Overview

1.3

Block Diagram

Figure 1.2 shows a block diagram.

Figure 1.2

Block Diagram

SCIi × 1 channel

RSPIc × 1 channel

MTU3d × 9 channels

GPTW × 10 channels

HRPWM

BSC

Clock

generation

circuit

RX CPU

RAM

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

Port 8

Port 9

Port A

Port B

Port C

DTCa

DMACAa ×

8 channels

ICUC

Port D

Port E

Port F

Port G

Port H

MPU

RAM with

ECC

12-bit DAC × 2 channels

CMT × 4 channels

TMR × 8 channels

POEG

POE3B

RIICa × 1 channel

CAN × 1 channel

USBb × 1 port

SCIh × 1 channel

CRCA

DOC

CAC

IWDTa

WDTA

ELC

Trusted Secure IP*1

E2 Data flash memory

Comparator C × 6 channels

ROM

Port K

SCIj × 5 channels

Temperature sensor

Sample and hold circuit

× 6 channels

12-bit A/D converter × 30 channels

Programmable gain amplifier

× 6 channels

ROM

Cache

ICUC:

Interrupt controller

DTCa:

Data transfer controller

WDTA:

Watchdog timer

IWDTa:

Independent watchdog timer

CRCA:

CRC (cyclic redundancy check) calculator

SCIj, SCIh, SCIi: Serial communications interface

RSPIc:

Serial peripheral interface

Trusted Secure IP:Encryption engine*1

RIICa:

I2C bus interface

MTU3d:

Multi-function timer pulse unit 3

GPTW:

General-purpose PWM timer W

POE3B:

Port output enable 3

CMT:

Compare match timer

TMR:

8-bit timer

DOC:

Data operation circuit

CAC:

Clock frequency accuracy measurement circuit

CAN:

CAN module

POEG:

Port output enable for GPTW

HRPWM:

High resolution PWM

ELC:

Event link controller

USBb:

USB2.0 FS host/function module

Note 1. Optional

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