R5F566TFCDFB datasheet(18/151 Pages) RENESAS

18 / 151 page

R01DS0315EJ0130 Rev.1.30

Page 18 of 151

Oct 06, 2023

RX66T Group

1. Overview

Bus control

BC0#, BC1#

Output

Strobe signals which indicate that either group of data bus pins

(D7 to D0, D15 to D8) is valid in access to the external bus

interface space, in 1-write strobe mode

ALE

Output

Address latch signal when address/data multiplexed bus is

selected

WAIT#

Input

Input pin for wait request signals in access to the external space

CS0# to CS3#

Output

Select signals for CS areas

Interrupt

NMI

Input

Non-maskable interrupt request pin

IRQ0 to IRQ15

Input

Maskable interrupt request pins

IRQ0-DS to IRQ15-DS

Input

Maskable interrupt request pins or pins which can also be used

as triggers for release from deep software standby

Multi-function timer pulse

unit 3

MTIOC0A, MTIOC0B,

MTIOC0C, MTIOC0D

I/O

The TGRA0 to TGRD0 input capture input/output compare

output/PWM output pins

MTIOC0A#, MTIOC0B#,

MTIOC0C#, MTIOC0D#

I/O

The TGRA0 to TGRD0 input capture inverted input/output

compare inverted output/PWM inverted output pins.

MTIOC1A, MTIOC1B

I/O

The TGRA1 and TGRB1 input capture input/output compare

output/PWM output pins.

MTIOC1A#, MTIOC1B#

I/O

The TGRA1 and TGRB1 input capture inverted input/output

compare inverted output/PWM inverted output pins.

MTIOC2A, MTIOC2B

I/O

The TGRA2 and TGRB2 input capture input/output compare

output/PWM output pins.

MTIOC2A#, MTIOC2B#

I/O

The TGRA2 and TGRB2 input capture inverted input/output

compare inverted output/PWM inverted output pins.

MTIOC3A, MTIOC3B,

MTIOC3C, MTIOC3D

I/O

The TGRA3 to TGRD3 input capture input/output compare

output/PWM output pins.

MTIOC3A#, MTIOC3B#,

MTIOC3C#, MTIOC3D#

I/O

The TGRA3 to TGRD3 input capture inverted input/output

compare inverted output/PWM inverted output pins.

MTIOC4A, MTIOC4B,

MTIOC4C, MTIOC4D

I/O

The TGRA4 to TGRD4 input capture input/output compare

output/PWM output pins

MTIOC4A#, MTIOC4B#,

MTIOC4C#, MTIOC4D#

I/O

The TGRA4 to TGRD4 input capture inverted input/output

compare inverted output/PWM inverted output pins.

MTIC5U, MTIC5V, MTIC5W

Input

The TGRU5, TGRV5, and TGRW5 input capture input/external

pulse input pins

MTIC5U#, MTIC5V#,

MTIC5W#

Input

The TGRU5, TGRV5, and TGRW5 input capture inverted input/

external pulse inverted input pins.

MTIOC6A, MTIOC6B,

MTIOC6C, MTIOC6D

I/O

The TGRA6 to TGRD6 input capture input/output compare

output/PWM output pins

MTIOC6A#, MTIOC6B#,

MTIOC6C#, MTIOC6D#

I/O

The TGRA6 to TGRD6 input capture inverted input/output

compare inverted output/PWM inverted output pins.

MTIOC7A, MTIOC7B,

MTIOC7C, MTIOC7D

I/O

The TGRA7 to TGRD7 input capture input/output compare

output/PWM output pins

MTIOC7A#, MTIOC7B#,

MTIOC7C#, MTIOC7D#

I/O

The TGRA7 to TGRD7 input capture inverted input/output

compare inverted output/PWM inverted output pins.

MTIOC9A, MTIOC9B,

MTIOC9C, MTIOC9D

I/O

The TGRA9 to TGRD9 input capture input/output compare

output/PWM output pins

MTIOC9A#, MTIOC9B#,

MTIOC9C#, MTIOC9D#

I/O

The TGRA9 to TGRD9 input capture inverted input/output

compare inverted output/PWM inverted output pins.

MTCLKA, MTCLKB, MTCLKC,

MTCLKD

Input

Input pins for the external clock.

MTCLKA#, MTCLKB#,

MTCLKC#, MTCLKD#

Input

Inverted input pins for the external clock.

ADSM0, ADSM1

Output

A/D conversion start request frame synchronization signal

output pins.

Table 1.4

Pin Functions (2/6)

Classifications

Pin Name

I/O

Description

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