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MK5027DIP 数据表(PDF) 1 Page - STMicroelectronics |
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MK5027DIP 数据表(HTML) 1 Page - STMicroelectronics |
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1 / 19 page ![]() MK5027 SS7 SIGNALLING LINK CONTROLLER August 1989 CMOS FULLY COMPATIBLE WITH BOTH 8 OR 16 BIT SYSTEMS SYSTEM CLOCK RATE TO 10MHz. DATA RATE UP TO 2.5Mbps FOR SS7 PROTOCOL PROCESSING,7Mbps FOR TRANSPARENT HDLC MODE COMPLETE LEVEL 2 IMPLEMENTATION COMPATIBLE WITH 1988 CCITT, AT&T, ANSI, AND BELLCORE SIGNALLING SYS- TEM NUMBER 7 LINK LEVEL PROTOCOLS 52 PIN PLCC AND 48-PIN DIP PIN-FOR-PIN COMPATIBLE WITH THE SGS-THOMSON X.25 CHIP (MK5025) AND NEARLY PIN-FOR- PIN COMPATIBLE WITH THE SGS-THOM- SON VLANCE CHIP (MK5032) BUFFER MANAGEMENT INCLUDES: - Initialization Block - Separate Receive and Transmit Rings - Variable Descriptor Ring and Window Sizes. ON CHIP DMA CONTROL WITH PROGRAM- MABLE BURST LENGTH SELECTABLE BEC OR PCR RETRANSMIS- SION METHODS, INCLUDING FORCED RE- TRANSMISSION FOR PCR HANDLES ALL 7 SS7 TIMERS HANDLES ALL SS7 FRAME FORMATTING: - Zero bit insert and delete - FCS generation and detection - Frame delimiting with flags PROGRAMMABLE MINIMUM SIGNAL UNIT SPACING (number of flags between SU’s) HANDLES ALL SEQUENCING AND LINK CONTROL SELECTABLE FCS OF 16 OR 32 BITS. TESTING FACILITIES: - Internal Loopback - Silent Loopback - Optional Internal Data Clock Generation - Self Test ALL INPUTS AND OUTPUTS ARE TTL COM- PATIBLE PROGRAMMABLE FOR FULL OR HALF DU- PLEX OPERATION DESCRIPTION The SGS-THOMSON Signalling System #7 Sig- nalling Link Controller (MK5027) is a VLSI semi- conductor device which provides a complete link control function conforming to the 1988 CCITT version of SS7. This includes frame formatting, transparency (so called ”bit-stufling”), error recov- ery by two types of retransmission, error monitor- ing, sequence number control, link status con- trol, and FISU generation. One of the outstanding features of the MK5027 is its buffer management which includes on-chip DMA. This feature allows users to handlq multiple packets of receive and transmit data at a time. (A conventional data link- control chip plus a separate DMA chip would han- dle data for only a single block at a time.) The MK5027 may be used with any of several popular 16 and 8 bit microprocessors, such as 68000, 6800, Z8000, Z80, LSI-11, 8086, 8088, 8080, etc. DIP48 PLCC52 VSS-GND DAL07 DAL06 DAL05 DAL04 DAL03 DAL02 DAL01 DAL00 READ INTR DALI DALO DAS BMO, BYTE, BUSREL BMI, BUSAKO HOLD, BUSRQ ALE, AS CS ADR READY RESET VSS-GND 24 HLDA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 48 47 46 45 44 43 42 41 40 39 38 37 36 23 22 21 20 19 18 17 16 15 35 34 33 32 31 30 29 28 27 26 25 TCLK A18 A19 A20 A21 A22 A23 RD DSR, CTS TD SYSCLK RCLK DTR, RTS VCC (+5V) DAL08 DAL09 DAL10 DAL11 DAL12 DAL13 DAL14 DAL15 A16 A17 M K 5 0 H 2 5 Figure 1: Pin Connection. 1/19 |
类似零件编号 - MK5027DIP |
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类似说明 - MK5027DIP |
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