C

L

0.4 mA

CR

CR

CR

CR 1

2

3

4

R1 = 1.2K

CR1 - CR4 = 1N914 or EQUIV

TEST

POINT

FROM

OUTPUT

UNDER

TEST

R1 = 1.4K

C

L

Vcc

Vcc

C = 50pF min @ 1 MHz

L

FROM

OUTPUT

UNDER

TEST

NOTE: This load is used on all outputs except INTR, HOLD, READY.

NOTE: This load is used on open

drain outputs INTR, HOLD, READY.

RCLK

13

15

14

16

17

21

20

19

18

RD

12

6

87

10

11

9

TD

TCLK

”0”

O.8 V

O.8 V

90 %

”1 ”

2.0 V

2.0 V

10 %

OUTPUT

INPUT

FLOAT

TIMING MEASUREMENTS ARE MADE AT THE FOLLOWING VOLTAGES,

UNLESS OTHERWISE SPECIFIED:

Figure 6: MK5027 Serial Link Timing Diagram

Figure 5A: TTL Output Load Diagram.

Figure 5B: Open Drain Output Load Diagram.

MK5027

13/19