PSD211R datasheet(22/51 Pages) STMICROELECTRONICS

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PSD211R Family

12.

Control Signals

(Cont.)

Signal State Just

Signal State

After Reset

Port

Configured Mode of Operation

During Reset

(Note 1)

AD0/A0-

All

Input (Hi-Z)

MCU address

AD15/A15

and/or data

MCU I/O

Input (Hi-Z)

Port Pins

PSD211R,

Logic 0

MCU address

PA0-PA7

Latched Address Out

ZPSD211R

ZPSD211RV

Hi-Z

MCU address

MCU I/O

Input (Hi-Z

Input (Hi-Z)

Chip Select Outputs,

PSD211R,

Logic 1

Per CS equations

Port Pins

CS0-CS7, CMOS

ZPSD211R

PB0-PB7

ZPSD211RV

Hi-Z

Per CS equations

Chip Select Outputs,

PSD211R,

Hi-Z

Per CS equations

CS0-CS7, Open Drain

ZPSD211R

ZPSD211RV

Hi-Z

Per CS equations

Address or Logic Inputs, A16-A18

Input (Hi-Z)

Port Pins

Chip Select Outputs,

PSD211R,

Logic 1

Per CS equations

PC0-PC2

CS8-CS10, CMOS

ZPSD211R

ZPSD211RV

Hi-Z

Per CS equations

Table 8A. External PSD Signal States During and Just After Reset

NOTE: 1. Signal is valid immediately after reset for non-V devices. ZPSD211RV devices need an additional

500 nsec after reset before signal is valid.

Internal

Internal Signal

Signal State

State During

During

Component

Internal Signal

Reset

Power-Down

CS0-CS10

Logic 1 (inactive)

Per CS Equations

PAD A and PAD B

CSIOPORT,

Per equations

ES0-ES7

Logic 0 (inactive)

for each

internal signal

All registers in CSIOPORT

N/A

address space, including:

Direction

Logic 0 in all bit of

Logic 0 until

Data

all registers

changed by MCU

PMR (turbo bit, ZPSD only)

Table 8B. Internal PSD Signal States During and Just After Reset

NOTE: N/A = Not Applicable

RESET LOW

VIH

RESET HIGH

ZPSD211R(V)

IS OPERATIONAL

500 ns

VIL

Figure 8. The Required Reset Cycle for ZPSD211RV Devices Only.

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