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PSD934210MIT 数据表(PDF) 49 Page - STMicroelectronics |
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PSD934210MIT 数据表(HTML) 49 Page - STMicroelectronics |
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49 / 89 page  49/89 PSD834F2V Direction Register. The Direction Register, in conjunction with the output enable (except for Port D), controls the direction of data flow in the I/O Ports. Any bit set to 1 in the Direction Register causes the corresponding pin to be an output, and any bit set to 0 causes it to be an input. The default mode for all port pins is input. Table 22. Port Pin Direction Control, Output Enable P.T. Not Defined Table 23. Port Pin Direction Control, Output Enable P.T. Defined Table 24. Port Direction Assignment Example Figure 25 and Figure 26 show the Port Architec- ture diagrams for Ports A/B and C, respectively. The direction of data flow for Ports A, B, and C are controlled not only by the direction register, but also by the output enable product term from the PLD AND Array. If the output enable product term is not active, the Direction Register has sole con- trol of a given pin’s direction. An example of a configuration for a Port with the three least significant bits set to output and the re- mainder set to input is shown in Table 24. Since Port D only contains three pins (shown in Figure 28), the Direction Register for Port D has only the three least significant bits active. Drive Select Register. The Drive Select Register configures the pin driver as Open Drain or CMOS for some port pins, and controls the slew rate for the other port pins. An external pull-up resistor should be used for pins configured as Open Drain. A pin can be configured as Open Drain if its corre- sponding bit in the Drive Select Register is set to a 1. The default pin drive is CMOS. Note that the slew rate is a measurement of the rise and fall times of an output. A higher slew rate means a faster output response and may create more electrical noise. A pin operates in a high slew rate when the corresponding bit in the Drive Reg- ister is set to 1. The default rate is slow slew. Table 25 shows the Drive Register for Ports A, B, C, and D. It summarizes which pins can be config- ured as Open Drain outputs and which pins the slew rate can be set for. Port Data Registers The Port Data Registers, shown in Table 26, are used by the MCU to write data to or read data from the ports. Table 26 shows the register name, the ports having each register type, and MCU access for each register type. The registers are described below. Table 25. Drive Register Pin Assignment Note: 1. NA = Not Applicable. Direction Register Bit Port Pin Mode 0 Input 1 Output Direction Register Bit Output Enable P.T. Port Pin Mode 0 0 Input 0 1 Output 1 0 Output 1 1 Output Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 1 1 1 Drive Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Port A Open Drain Open Drain Open Drain Open Drain Slew Rate Slew Rate Slew Rate Slew Rate Port B Open Drain Open Drain Open Drain Open Drain Slew Rate Slew Rate Slew Rate Slew Rate Port C Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Port D NA1 NA1 NA1 NA1 NA1 Slew Rate Slew Rate Slew Rate |
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