PSD934210MIT datasheet(6/89 Pages) STMICROELECTRONICS

6 / 89 page

PSD834F2V

6/89

KEY FEATURES

A simple interface to 8-bit microcontrollers that

use either multiplexed or non-multiplexed

busses. The bus interface logic uses the control

signals generated by the microcontroller

automatically when the address is decoded and

a read or write is performed. A partial list of the

MCU families supported include:

– Intel 8031, 80196, 80186, 80C251, and

80386EX

– Motorola 68HC11, 68HC16, 68HC12, and

683XX

– Philips 8031 and 8051XA

– Zilog Z80 and Z8

Internal 2 Mbit Flash memory. This is the main

Flash memory. It is divided into 8 equal-sized

blocks that can be accessed with user-specified

addresses.

Internal secondary 256 Kbit Flash boot memory.

It is divided into 4 equal-sized blocks that can be

accessed with user-specified addresses. This

secondary memory brings the ability to execute

code and update the main Flash

concurrently.

Internal 64 Kbit SRAM. The SRAM’s contents

can be protected from a power failure by

connecting an external battery.

CPLD with 16 Output macrocells (OMCs) and

24 Input macrocells (IMCs). The CPLD may be

used to efficiently implement a variety of logic

functions for internal and external control.

Examples include state machines, loadable

shift registers, and loadable counters.

Decode PLD (DPLD) that decodes address for

selection of internal memory blocks.

27 individually configurable I/O port pins that

can be used for the following functions:

– MCU I/Os

–PLD I/Os

– Latched MCU address output

– Special function I/Os.

– 16 of the I/O ports may be configured as

open-drain outputs.

Standby current as low as 25 µA.

Built-in JTAG compliant serial port allows full-

chip In-System Programmability (ISP). With it,

you can program a blank device or reprogram a

device in the factory or the field.

Internal page register that can be used to

expand the microcontroller address space by a

factor of 256.

Internal programmable Power Management

Unit (PMU) that supports a low power mode

called Power Down Mode. The PMU can

automatically detect a lack of microcontroller

activity and put the PSD into Power-down

mode.

Erase/Write cycles:

– Flash memory – 100,000 minimum

– PLD – 1,000 minimum

– Data Retention: 15 year minimum (for Main

Flash memory, Boot, PLD and Configuration

bits)

PSD934210MIT 数据表(PDF) 6 Page - STMicroelectronics

PSD934210MIT 数据表(HTML) 6 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89

数据表下载