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TDA7572 数据表(PDF) 21 Page - STMicroelectronics |
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TDA7572 数据表(HTML) 21 Page - STMicroelectronics |
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21 / 64 page ![]() TDA7572 Electrical specifications 21/64 4.3.4 Oscillator Table 9. Oscillator Symbol Parameters Test conditions Min. Typ. Max. Units Internal oscillator FPWM_NOM Switching frequency PWMCLOCK=[0 1] 100K 120 140K KHz PWMCLOCK=[1 0] FPWM_NOM *2 PWMCLOCK=[0 0] FPWM_NOM /2 CLKDC Duty cycle 48 50 52 % VCLK_High Maximum voltage level Clock output high value Load = 20Kohm and 100pF to buffered SVR VP25-0.1 VP25 V VCLK_Low Minimum voltage level Clock output low value Load = 20Kohm and 100pF to buffered SVR VM25-0.1 VM25 V VCLK-P-P Peak-peak voltage Load = 20Kohm and 100pF to SVR -10% 4.7 +10% V Dither cap charge current Dither pin voltage= 2.5V -20% 100 +20% µA Dither cap discharge current -20% 100 +20% µA Peak-peak dither voltage swing 1.4 1.6 1.7 V Dither external clock determination Voltage at the dither pin at to select external clock function VDIG-0.2 V No dither Voltage at the dither pin at which no dither will occur VDGND +0.2 V Peak FPWM increase due to dither Cdither=100nF +8 +10 +12 % Peak FPWM decrease due to dither Cdither=100nF -8 -10 -12 % Triangular peak value VGND+ 1V VDIG- 1V |
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