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TDA7572 数据表(PDF) 22 Page - STMicroelectronics |
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TDA7572 数据表(HTML) 22 Page - STMicroelectronics |
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22 / 64 page ![]() Electrical specifications TDA7572 22/64 4.3.5 Modulator 4.3.6 Gate drive and output stage control Table 10. Modulator Symbol Parameters Test conditions Min. Typ. Max. Units Integrator op. amp. Int_Voff Input offset voltage -2.5 +2.5 mV Int_ibias Input bias current Guaranteed by design 500 nA Toff Maximum duty cycle Vsp =1 4.4 1.1 µs Table 11. Gate drive and output stage control Symbol Parameters Test conditions Min. Typ. Max. Units VOL_LSD LSG low voltage Isink = 0.5A Isink = 20mA 1.75 0.080 V VOH_LSD LSG high voltage Isource = 0.5A Isource = 20mA 7 9.2 V VOL_HSD HSG low voltage Isink = 0.5A Isink = 20mA VSP-7 VSP- 9.2 V VOH_HSD HSG high voltage Isource = 0.5A Isource = 20mA VSP- 1.75 VSP- 0.080 V HSG low Z drive tdelay After a commutation 2 10 µs LSG low Z drive tdelay After a commutation 2 10 µs HSG HiZ sink current VHSG=VSP t>5uS 150 mA LSG HiZ source current VLSG=VSM , t>5uS 150 mA Overcurrent sensing IlimThresh Range of Ilim Trthresh 0.3 1.1 V Vilim Vilim Engagement of the current limiting VlimitTreshold=1V w.r.t. VM2p5 Vlim* 3.0 Vlim* 5.0 V Vitrip Start of cycle by cycle current limiting -15% Vlim * 6.0 +15% V Anti-shoo through PVGS_ON PFET gate voltage that will block NFET enhancement -2.5 V PVGS_OFF PFET gate voltage that will allow NFET enhancement -3.5 V |
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