ST10F168-Q3 datasheet(71/74 Pages) STMICROELECTRONICS

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ST10F168

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20.5.13 - External Bus Arbitration

VDD = 5V ± 10%, VSS = 0V, for Q6 version : TA = -40, +85°C and for Q3 version TA = -40, +125°C, CL = 100pF,

unless otherwise specified.

Note: 1. Partially tested, guaranted by design characterization.

Notes: 1. The ST10F168 will complete the currently running bus cycle before granting bus access.

2. This is the first possibility for BREQ to become active.

3. The CS outputs will be resistive high (pullup) after t64.

Symbol

Parameter

Max. CPU Clock

25MHz

Variable CPU Clock

1/2 TCL = 1 to 25MHz

Unit

Minimum

Maximum

Minimum

Maximum

t61 SR HOLD input setup time to CLKOUT

–

t62 CC CLKOUT to HLDA high or BREQ low delay

–

t63 CC CLKOUT to HLDA low or BREQ high delay

–

t64 CC CSx release

–

t65 CC CSx drive

-4

t66 CC Other signals release

–

t67 CC Other signals drive

-4

Figure 30 : External bus arbitration, releasing the bus

t61

t63

t66

t64

t62

CLKOUT

HOLD

HLDA

BREQ

Others

CSx

(P6.x)

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