ST10F168-Q3 datasheet(13/74 Pages) STMICROELECTRONICS

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ST10F168

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5 - FLASH MEMORY

The

ST10F168

provides

256K

Byte

electrically erasable and reprogrammable Flash

Memory on-chip.

The Flash Memory can be used both for code and

data storage. It is organized into four 32-bit wide

blocks allowing even double Word instructions to

be fetched in one machine cycle. The four blocks

of size16K, 48K, 96K and 96K Byte can be erased

and reprogrammed individually (see Table 2 and

Table 3).

The Flash Memory can be programmed in a pro-

gramming board or in the target system which

provides high system flexibility. The algorithms to

program or erase the flash memory are embed-

ded in the Flash Memory itself (ST Embedded

Algorithm Kernel, or STEAKTM).

To start a program / erase operation, the user’s

software has just to load GPRs with the address

and data to be programmed, or sector to be

erased. STEAK uses embedded routines, which

check the validity of the programmed parameters,

decode and then execute the programming or

erase command. During operation, the STEAK

routines carry out checks and retries to verify

proper cell programming or erasing. When an

error occurs, STEAK returns an error-code which

identifies the cause of the error.

A Flash Memory protection option prevents the

read-back of the Flash Memory contents from

external memory, or from on-chip RAM. Code

operation from within the Flash continues as nor-

mal.

The first bank (16K Byte) and part of the second

bank (16K Byte out of 48K Byte) of the on-chip

Flash Memory of the ST10F168 can be mapped

to either segment 0 (addresses 00000h to

07FFFh) or to segment 1 (addresses 10000h to

17FFFh) during the initialization phase. External

memory can be used for additional system

flexibility.

VDD = 5V ± 10%, VPP = 12V ± 5%, VSS = 0V, fCPU = 25MHz, for Q6 version : TA = -40°C, +85°C and for

Q3 version TA = -40°C, + 125°C.

Table 2 : Flash Memory Characteristics

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

fCPU

CPU Frequency during

erasing / programming operation

MHz

Cyc

Erasing / Programming Cycles

fCPU = 25MHz

10K

tSPRG

Single Word Programming Time

fCPU = 25MHz

1500

µs

tDPRG

Double Word Programming Time

fCPU = 25MHz

1500

µs

tEBNK

Sector Erasing Time

fCPU = 25MHz

315

tRET

Data Retention Time

Defectivity below 1ppm / year

year

Table 3 : Flash Memory Bank Organisation

Bank

Addresses (segment 0)

Addresses (segment 1)

Size (Byte)

000000h to 003FFFh

004000h to 007FFFh + 018000h to 01FFFFh

020000h to 037FFFh

038000h to 04FFFFh

010000h to 013FFFh

014000h to 01FFFFh

020000h to 03FFFFh

038000h to 04FFFFh

16K

48K

96K

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