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ST10F168-Q3 数据表(PDF) 51 Page - STMicroelectronics |
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ST10F168-Q3 数据表(HTML) 51 Page - STMicroelectronics |
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51 / 74 page  ST10F168 51/74 Notes: 1. ST10F168 pins are equipped with low-noise output drivers which significantly improve the device’s EMI performance. These low-noise drivers deliver their maximum current only until the respective target output level is reached. After this, the output current is reduced. This results in increased impedance of the driver, which attenuates electrical noise from the connected PCB tracks. The current specified in column “Test Conditions” is delivered in all cases. 2. This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the voltage results from the external circuitry. 3. Partially tested, guaranteed by design characterization. 4. Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin exceeds the specified range (i.e. VOV > VDD+0.5V or VOV < -0.5V). The absolute sum of input overload currents on all port pins may not exceed 50mA. The supply voltage must remain within the specified limits. 5. The maximum current may be drawn while the respective signal line remains inactive. 6. This specification is only valid during Reset, or during Hold-mode or Adapt-mode. Port 6 pins are only affected if they are used for CS output and the open drain function is not enabled. 7. The minimum current must be drawn in order to drive the respective signal line active. 8. The power supply current is a function of the operating frequency. This dependency is illustrated in the Figure 15. These parameters are tested at VDDmax and 25MHz CPU clock with all outputs disconnected and all inputs at VIL or VIH. The chip is configured with a demultiplexed 16-bit bus, direct clock drive, 5 chip select lines and 2 segment address lines, EA pin is low during reset. After reset, Port 0 is driven with the value ‘00CCh’ that produces infinite execution of NOP instruction with 15 wait-state, R/W delay, memory tristate wait state, normal ALE. Peripherals are not activated. 9. Idle mode supply current is a function of the operating frequency. This dependency is illustrated in the Figure 15. These parameters are tested at VDDmax and 25MHz CPU clock with all outputs disconnected and all inputs at VIL or VIH. 10. This parameter value includes leakage currents. With all inputs (including pins configured as inputs) at 0 V to 0.1V or at VDD – 0.1V to VDD, VREF = 0V, all outputs (including pins configured as outputs) disconnected. 11. Apply 12V on VPP 10ms after VDD is stable at power up. VPP pin must be switched to 0V before to switch off VDD (5V). IOZ2 CC Input leakage current (all other) 0V < VIN < VDD – ±1 µA IOV SR Overload current 3 4 – ±5mA RRST CC RSTIN pull-up resistor 3 0V < VIN < VILmax 50 250 k Ω IRWH 5 Read / Write inactive current 6 VOUT = 2.4V – -40 µA IRWL 7 Read / Write active current 6 VOUT = VOLmax -500 – µA IALEL 6 ALE inactive current 6 VOUT = VOLmax 40 – µA IALEH 6 ALE active current 6 VOUT = 2.4V – 600 µA IP6H 6 Port 6 inactive current 6 VOUT = 2.4V – -40 µA IP6L 7 Port 6 active current 6 VOUT = VOL1max -500 – µA IP0H 6 Port 0 configuration current 6 VIN = VIHmin –-10 µA IP0L 7 VIN = VILmax -100 – µA IIL CC XTAL1 input current 0V < VIN < VDD – ±20 µA CIO CC Pin capacitance 6 (digital inputs / outputs) f = 1MHz, TA = 25°C –10 pF ICC Power supply current RSTIN = VIH1 fCPU in [MHz] 8 – 20 + 6 x fCPU mA IID Idle mode supply current RSTIN = VIH1 fCPU in [MHz] 9 – 20 + 3 x fCPU mA IPD Power-down mode supply current VDD = 5.5V 10 –100 µA IPPR VPP Read Current VPP < VDD –200 µA IPPW VPP Programming / Erasing Current 3 VPP = 12V, fCPU = 25MHz –20 mA VPP 11 VPP during Programming / Erasing Operations 11,4 12,6 V Symbol Parameter Test Conditions Min. Max. Unit |
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