ST10F168-Q3 datasheet(11/74 Pages) STMICROELECTRONICS

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ST10F168

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4 - MEMORY ORGANIZATION

The memory space of the ST10F168 is configured

in a Von Neumann architecture. Code memory,

data memory, registers and I/O ports are orga-

nized within the same linear address space of

16M Byte. The entire memory space can be

accessed bytewise or wordwise. Particular por-

tions of the on-chip memory have additionally

been made directly bit addressable.

FLASH: 256K Byte of on-chip Flash memory. See

Flash Memory on page 13

IRAM:

Byte

on-chip

internal

RAM

(dual-port) is provided as a storage for data, sys-

tem stack, general purpose register banks and

code. A register bank is 16 wordwide (R0 to R15)

and / or bytewide (RL0, RH0, …, RL7, RH7) gen-

eral purpose registers.

XRAM: 6K Byte of on-chip extension RAM (single

port XRAM) is provided as a storage for data, user

stack and code. The XRAM is connected to the

internal XBUS and is accessed like an external

memory in 16-bit demultiplexed bus-mode without

wait state or read / write delay (80ns access at

25MHz CPU clock). Byte and Word access are

allowed.

The

XRAM

address

range

00’D000h

00’E7FFh if the XRAM is enabled (XPEN bit 2 of

SYSCON register). As the XRAM appears like

external memory, it cannot be used for the

ST10F168’s system stack or register banks. The

XRAM is not provided for single bit storage and

therefore is not bit addressable. If bit XPEN is

cleared, then any access in the address range

00’D000h - 00’E7FFh will be directed to external

memory interface, using the BUSCONx register

corresponding to address matching ADDRSELx

SFR/ESFR: 1024 Byte (2 x 512 Byte) of address

space is reserved for the Special Function Regis-

ter areas. SFRs are wordwide registers which are

used for controlling and monitoring functions of

the different on-chip units.

CAN: Address range 00’EF00h - 00’EFFFh is

reserved for the CAN Module access. The CAN is

enabled by setting XPEN bit 2 of the SYSCON

tiplexed addresses and a 16-bit data bus (Byte

accesses are possible). Two wait states give an

access time of 160ns at 25MHz CPU clock. No

tristate wait state is used.

Note: If the CAN module is used, Port 4 can not

be programmed to output all 8 segment

address lines. Therefore, only 4 segment

address lines can be used, reducing the

external memory space to 5M Byte (1M

Byte per CS line)

To meet the needs of designs where more mem-

ory is required than is provided on chip, up to 16M

Byte of external RAM and / or ROM can be con-

nected to the microcontroller.

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