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ST10R272L 数据表(PDF) 76 Page - STMicroelectronics |
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ST10R272L 数据表(HTML) 76 Page - STMicroelectronics |
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76 / 77 page  76/77 ST10R272L - ELECTRICAL CHARACTERISTICS 1 The transition of shift and latch edge of SSPCLK is programmable. This figure uses the falling edge as shift edge (drawn bold). 2 The bit timing is repeated for all bits to be transmitted or received. 3 The active level of the chip enable lines is programmable. This figure uses an active low CE (drawn bold). At the end of a transmission or reception the CE signal is disabled in sin- gle transfer mode. In continuous transfer mode it remains active. Figure 29 SSP write timing Figure 30 SSP read timing t 204 t 203 SSPCLK SSPCEx SSPDAT t 205 t 207 t 207 t 207 t 208 t 209 t 206 1st Bit Last Bit 2nd Bit t 200 t 201 t 202 1) 3) 2) t 211 SSPCLK SSPCEx SSPDAT t 209 t 206 last Wr. Bit Lst.In Bit 1) 3) 2) t 212 1st.In Bit t 210 |
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