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ST10R272L - PARALLEL PORTS

PARALLEL PORTS

The ST10R272L provides up to 77 I/O lines organized into 7 input/output ports and one input

port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise)

programmable as inputs or outputs by direction registers. The I/O ports are true bidirectional

ports which are switched to high impedance state when configured as inputs. The output

drivers of three I/O ports can be configured (pin by pin) for push/pull operation or open-drain

operation by control registers. During the internal reset, all port pins are configured as inputs.

All port lines have programmable alternate input or output functions associated with them.

PORT0 and PORT1 may be used as address and data lines when accessing external

memory, while Port 4 outputs the additional segment address bits A23/19/17...A16 in systems

where segmentation is enabled to access more than 64 KBytes of memory. Port 6 provides

optional bus arbitration signals (BREQ, HLDA, HOLD) and chip select signals. Port 3 includes

alternate functions of timers, serial interfaces, the optional bus control signal BHE and the

system clock output (CLKOUT). Port 5 is used for timer control signals. Port 2 lines can be

used as fast external interrupt lines. Port 7 includes alternate function for the PWM signal. All

port lines that are not used for these alternate functions may be used as general purpose I/O

lines.

EXTERNAL BUS CONTROLLER

All external memory accesses are performed by the on-chip External Bus Controller which

can be programmed either to single chip mode when no external memory is required, or to the

following external memory access modes:

In the demultiplexed bus modes, addresses are output on PORT1 and data is input/output on

PORT0/P0L, respectively. In the multiplexed bus modes both addresses and data use PORT0

for input/output.

Memory cycle time, memory tri-state time, length of ALE and read write delay are

programmable so that a wide range of different memory types and external peripherals can be

used. Up to 4 independent address windows can be defined (via ADDRSELx / BUSCONx

windows are arranged hierarchically where BUSCON4 overrides BUSCON3 etc. All accesses

to locations not covered by these 4 address windows are controlled by BUSCON0. Up to 5

external CS signals (4 windows plus default) can be generated to reduce external glue logic.

Access to very slow memories is supported by the READY function.

A HOLD/HLDA protocol is available for bus arbitration so that external resources can be

shared with other bus masters. In slave mode, the slave controller can be connected to an-

other master controller without glue logic. For applications which require less than 16 MBytes

16-bit data, demultiplexed

16-/18-/20-/24-bit addresses

16-bit data, multiplexed

16-/18-/20-/24-bit addresses

8-bit data, multiplexed

16-/18-/20-/24-bit addresses

8-bit data, demultiplexed

16-/18-/20-/24-bit addresses

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