ST10R272L datasheet(61/77 Pages) STMICROELECTRONICS

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ST10R272L - ELECTRICAL CHARACTERISTICS

Data hold after RdCS

t51

–0

–

Data float after RdCS

(with RW-delay)1 2

t53

–

13 +

tF +

2tA

–2TCL - 7

tF + 2tA

Data float after RdCS

(no RW-delay)1 2

t68

–

3 +

tF+ 2tA

–TCL - 7

tF + 2tA

Address hold after

RdCS, WrCS

t55

-5 +

–

-5 +

–ns

Data hold after WrCS

t57

3 +

–

TCL - 7 +

–ns

1) Output loading is specified using Figure 13 with CL = 5 pF.

2) This delay assumes that the following bus cycle is a demultiplexed bus cycle and that the

data bus will only be driven externally when the RD or RdCs signal becomes active. RW-

delay and

A refer to the following bus cycle. If the following bus cycle is a muxtiplexed bus

cycle, refer to equivalent multiplexed AC timing (which are still applicable due to automatic

insertion an idle state (2TCL) when switching from Demultiplexed to Multiplexed Bus Mode.

Parameter

Symbol

Max CPU Clock 50MHz

Variable CPU Clock

1/2TCL = 1 to 50 MHz

min.

max.

min.

max.

Table 18 Demultiplexed bus

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