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ST10R272L - ELECTRICAL CHARACTERISTICS

16.3.1

CPU Clock Generation Mechanisms

ST10R272L internal operation is controlled by the CPU clock fCPU. Both edges of the CPU

clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations. The external

timing (AC Characteristics) specification therefore depends on the time between two consec-

utive edges of the CPU clock, called “TCL” (see figure below).

The CPU clock signal can be generated by different mechanisms. The duration of TCLs and

their variation (and also the external timing) depends on the fCPU generation mechanism. This

must be considered when calculating ST10R272L timing.

The CPU clock generation mechanism is set during reset by the logic levels on pins P0.15-13

(P0H.7-5).

Figure 14 CPU clock generation mechanisms

P0.15-13 (P0H.7-5)

CPU frequency

fCPU = fXTAL * F

External clock

input range 10-

50MHz

Notes

111

XTAL * 4

2.5 to 12.5 MHz

Default configuration

110

XTAL * 3

3.33 to 16.66 MHz

101

XTAL * 2

5 to 25 MHz

Table 15 CPU clock generation mechanisms

TCL TCL

fCPU

fXTAL

fCPU

fXTAL

Phase Locked Loop Operation (PLL factor=4)

Direct Clock Drive

TCL

fCPU

fXTAL

Prescaler Operation

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