ST10R272LT1 datasheet(13/77 Pages) STMICROELECTRONICS

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ST10R272L - CENTRAL PROCESSING UNIT

CENTRAL PROCESSING UNIT

The main core of the CPU contains a 4-stage instruction pipeline, a MAC multiply-

accumulation unit, a separate multiply and divide unit, a bit-mask generator and a barrel

shifter. Most instructions can be executed in one machine cycle requiring 40ns at 50MHz CPU

clock.

The CPU includes an actual register context consisting of 16 wordwide GPRs physically

located in the on-chip RAM area. A Context Pointer (CP) register determines the base

address of the active register bank to be accessed by the CPU. The number of register banks

is only restricted by the available internal RAM space. For easy parameter passing, one

A system stack of up to 1024 bytes is provided as a storage for temporary data. The system

stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer

(SP) register. Two separate SFRs, STKOV and STKUN, are compared against the stack

pointer value during each stack access to detect stack overflow or underflow.

Figure 4 CPU block diagram

Internal

RAM

1KByte

R15

General

Purpose

Registers

R15

MDH

MDL

Barrel-Shift

Mul./Div.-HW

Bit-Mask Gen.

ALU

16-Bit

Context Ptr

ADDRSEL 1

ADDRSEL 2

ADDRSEL 3

ADDRSEL 4

Code Seg. Ptr.

CPU

IDX0

IDX1

QX1

QX0

QR0

QR1

STKOV

STKUN

Exec. Unit

Instr. Ptr

Instr. Reg

4-Stage

Pipeline

PSW

SYSCON

BUSCON 0

BUSCON 1

BUSCON 2

BUSCON 3

BUSCON 4

Data Pg. Ptrs

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