ST10R272LT1 datasheet(21/77 Pages) STMICROELECTRONICS

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ST10R272L - MULTIPLY-ACCUMULATE UNIT (MAC)

of repetition that remains to complete the sequence. If the Repeat Unit is used in the interrupt

routine, MRW must be saved by the user and restored before the end of the interrupt routine.

Note

The Repeat Count should be used with caution. In this case MR should be written as

0. In general MR should not be set by the user otherwise correct instruction

processing can not be guaranteed.

MAC interrupt

The MAC can generate an interrupt according to the value of the status flags C (carry), SV

(overflow), E (extension) or SL (limit) of the MSW. The MAC interrupt is globally enabled when

the MIE flag in MCW is set. When it is enabled the flags C, SV, E or SL can triggered a MAC

interrupt when they are set provided that the corresponding mask flag CM, VM, EM or LM in

MCW is also set. A MAC interrupt request set the MIR flag in MSW, this flag must be reset by

the user during the interrupt routine otherwise the interrupt processing restarts when

returning from the interrupt routine.

The MAC interrupt is implemented as a Class B hardware trap (trap number Ah - trap priority

I). The associated Trap Flag in the TFR register is MACTRP, bit #6 of the TFR (Remember

that this flag must also be reset by the user in the case of an MAC interrupt request).

As the MAC status flags are updated (or eventually written by software) during the Execute

stage of the pipeline, the response time of a MAC interrupt request is 3 instruction cycles (see

Figure 3). It is the number of instruction cycles required between the time the request is sent

and the time the first instruction located at the interrupt vector location enters the pipeline.

Note that the IP value stacked after a MAC interrupt does not point to the instruction that

triggers the interrupt.

Figure 7 Pipeline diagram for MAC interrupt response time

N-1

N-2

N-3

N+1

N-1

N-2

N+2

N+1

N-1

N+4

TRAP (1)

N+2

N+1

TRAP (2)

TRAP (1)

N+2

TRAP (2)

TRAP (1)

N+3

N+2

N+1

FETCH

DECODE

EXECUTE

WRITEBACK

MAC Interrupt Request

Response Time

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