ST10R272LT6 datasheet(72/77 Pages) STMICROELECTRONICS

72 / 77 page

72/77

ST10R272L - ELECTRICAL CHARACTERISTICS

16.3.7

External Hardware Reset

VDD = 3.3 V ± 0.3 V

VSS = 0 V

TA = -40 to +85 °C

CL = 50 pF

Parameter

Symbol

Max. CPU Clock

= 50 MHz

Variable CPU Clock

1/2TCL = 1 to 50 MHz

min.

max.

min.

max.

Sync. RSTIN low time1)

1) On power-up reset, the RSTIN pin must be asserted until a stable clock signal is available

(about 10...50 ms to allow the on-chip oscillator to stabilize) and until System Start-up Con-

figuration is correct on PORT0 (about 50

µs for internal pullup devices to load 50 pF from

VILmin to VIHmin).

t70

–

4 TCL + 10

–

RSTIN low to internal

reset sequence start

t71

416

TCL

internal reset sequence,

(RSTIN internally pulled

low)

t72

1024

TCL

RSTIN rising edge to inter-

nal reset condition end

t73

46TCL

PORT0 system start-up

configuration setup to

RSTIN rising edge 2))

2) The value of bits 0 (EMU), 1 (ADAPT), 13 to 15 (Clock Configuration) are loaded during

hardware reset as long as internal reset signal is active, and have an immediate effect on

the system.

t74

100

–

100

–

PORT0 system start-up

configuration hold after

RSTIN rising edge

t75

16TCL

Bus signals drive from

internal reset end

t76

RSTIN low to signals

release

t77

–

ALE rising edge from inter-

nal reset condition end

t78

88TCL

Async. RSTIN low time1

t79

1500

–

1500

–

Table 21 External hardware reset

ST10R272LT6 数据表(PDF) 72 Page - STMicroelectronics

ST10R272LT6 数据表(HTML) 72 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77

数据表下载