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ST10R272LT6 数据表(PDF) 75 Page - STMicroelectronics |
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ST10R272LT6 数据表(HTML) 75 Page - STMicroelectronics |
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75 / 77 page ![]() 75/77 ST10R272L - ELECTRICAL CHARACTERISTICS 16.3.8 Synchronous Serial Port Timing V CC = 3.3 V ± 0.3 V V SS = 0 V TA = -40 to +85 °C C L = 50 pF Parameter Symbol Max. Baudrate = 25 MBd Variable Baudrate = 0.2 to 25 MBd min. max. min. max. SSP clock cycle time t200 CC 40 40 4 TCL 512 TCL ns SSP clock high time t201 CC 13 – t200/2 - 7 – ns SSP clock low time t202 CC 13 – t200/2 - 7 – ns SSP clock rise time t203 CC – 3 – 3 ns SSP clock fall time t204 CC – 3 – 3 ns CE active before shift edge t205 CC 13 – t200/2 - 7 – ns CE inactive after latch edge t206 CC 33 47 t200 - 7 t200 + 7 ns Write data valid after shift edge t207 CC – 7 – 7 ns Write data hold after shift edge t208 CC 0 – 0 – ns Write data hold after latch edge t209 CC 15 25 t200/2 - 5 t200/2 + 5 ns Read data active after latch edge t210 SR 27 – t200/2 + 7 – ns Read data setup time before latch edge t211 SR 15 – 15 – ns Read data hold time after latch edge t212 SR 0 – 0 – ns Table 22 Synchronous serial port timing |
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