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ST10R272LT6 数据表(PDF) 73 Page - STMicroelectronics |
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ST10R272LT6 数据表(HTML) 73 Page - STMicroelectronics |
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73 / 77 page ![]() 73/77 ST10R272L - ELECTRICAL CHARACTERISTICS 1 The ST10R272L is reset in its default state asynchronously with RSTIN. The internal RAM content may be altered if an internal write access is in progress. 2 On power-up, RSTIN must be asserted t79 after a stabilized CPU clock signal is available. 3 Internal pullup devices are active on the PORT0 lines, so - input level is high if the respec- tive pin is left open - or is low if the respective pin is connected to an external pulldown device. 4 The ST10R272L starts execution here at address 00’0000h. 5RSTOUT stays active until execution of the EINIT (end of initialization) instruction. 6 Activation of the IO pins is controlled by software Figure 27 External asynchronous hardware reset (power-up reset): Vpp low RSTIN PORT1 (Demux Bus) t76 PORT0 t75 4) Internal Reset Signal t73 3) t792) t74 ALE RD, WR RSTOUT 5) Other IOs 6) t77 t78 1) 1 |
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