ST10R272LT6 datasheet(33/77 Pages) STMICROELECTRONICS

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ST10R272L - SYSTEM RESET

SYSTEM RESET

The following type of reset are implemented on the ST10R272L:

Asynchronous hardware reset: Asynchronous reset does not require a stabilized clock

signal on XTAL1 as it is not internally resynchronized, it resets the microcontroller into its

default reset state. Asynchronous reset is required on chip power-up and can be used during

catastrophic situations. The rising edge of the RSTIN pin is internally resynchronized before

exiting the reset condition, therefore, only the entry to hardware reset is asynchronous.

Synchronous hardware reset (warm reset): A warm synchronous hardware reset is

triggered when the reset input signal RSTIN is latched low and Vpp pin is high. The I/Os are

immediately (asynchronously) set in high impedance, RSTOUT is driven low. After RSTIN

negation is detected, a short transition period elapses, during which pending internal hold

states are cancelled and any current internal access cycles are completed, external bus

cycles are aborted. Then, the internal reset sequence is active for 1024 TCL (512 CPU clock

cycles). During this reset sequence, if bit BDRSTEN was previously set by software (bit 5 in

SYSCON register), RSTIN pin is driven low and internal reset signal is asserted to reset the

microcontroller in its default state. Note that after all reset sequence, bit BDRSTEN is cleared.

After the reset sequence has been completed, the RSTIN input is sampled. When the reset

input signal is active at that time the internal reset condition is prolonged until RSTIN

becomes inactive.

Software reset: The reset sequence can be triggered at any time by the protected

instruction SRST (software reset). This instruction can be executed deliberately within a

program, e.g. to leave bootstrap loader mode, or on a hardware trap that reveals a system

failure. As for a synchronous hardware reset, the reset sequence lasts 1024 TCL (512 CPU

clock cycles), and drives the RSTIN pin low.

Watchdog timer reset: When the watchdog timer is not disabled during the initialization or

serviced regularly during program execution it will overflow and trigger the reset sequence.

Unlike hardware and software resets, the watchdog reset completes a running external bus

cycle if this bus cycle does not use READY, or if READY is sampled active (low) after the

programmed waitstates. When READY is sampled inactive (high) after the programmed

waitstates the running external bus cycle is aborted. Then the internal reset sequence is

started. The watchdog reset cannot occur while the ST10R272L is in bootstrap loader mode.

Bidirectional reset: This reset makes the watchdog timer reset and software reset

externally visible. It is active for the duration of an internal reset sequences caused by a

watchdog timer reset and software reset. Therefore, the bidirectional reset transforms an

internal watchdog timer reset or software reset into an external hardware reset with a

minimum duration of 1024 TCL.

ST10R272LT6 数据表(PDF) 33 Page - STMicroelectronics

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