Symbol

Alt

Parameter

Min

Max

Unit

(1)

Clock Rise Time

300

ns

(1)

Clock Fall Time

300

ns

(1)

SDA Rise Time

20

300

ns

(1)

SDA Fall Time

20

300

ns

(2)

Clock High to Input Transition

600

ns

Clock Pulse Width High

600

ns

Input Low to Clock Low (START)

600

ns

Clock Low to Input Transition

0

µs

Clock Pulse Width Low

1.3

µs

Input Transition to Clock Transition

100

ns

Clock High to Input High (STOP)

600

ns

Input High to Input Low (Bus Free)

1.3

µs

Clock Low to Data Out Valid

200

900

ns

Clock Low to Data Out Transition

200

ns

Clock Frequency

400

kHz

Write Time

10

ms

Notes: 1. Sampled only, not 100% tested.

2. For a reSTART condition, or following a write cycle.

Data Input. During data input the ST24LC21 sam-

ple the SDA bus signal on the rising edge of the

clock SCL. Note that for correct device operation

the SDA signal must be stable during the clock low

to high transition and the data must change ONLY

when the SCL line is low.

Memory Addressing. To start communication be-

tween the bus master and the slave ST24LC21, the

master must initiate a START condition. Following

this, the master sends onto the SDA bus line 8 bits

(MSB first) corresponding to the device select code

(7 bits) and a READ or WRITE bit. The 4 most

significant bits of the device select code are the

definition. For these memories the 4 bits are fixed

as 1010b. The following 3 bits are Don’t Care. The

8th bit sent is the read or write bit (RW), this bit is

set to ’1’ for read and ’0’ for write operations. If a

match is found, the corresponding memory will

acknowledge the identification on the SDA bus

during the 9th bit time.

Write Operations

Following a START condition the master sends a

device select code with the RW bit reset to ’0’. The

memory acknowledges this and waits for a byte

address. After receipt of the byte address the de-

vice again responds with an acknowledge.

VCLK = 0 will not modify data and will be acknow-

ledged on data bytes, as shown in Figure 11.

Byte Write. In the Byte Write mode the master

sends one data byte, which is acknowledged by the

memory. The master then terminates the transfer

by generating a STOP condition.

Page Write. The Page Write mode allows up to 8

bytes to be written in a single write cycle, provided

that they are all located in the same ’row’ in the

memory: that is the most significant memory ad-

dress bits are the same. The master sends from

one up to 8 bytes of data, which are each acknow-

ledged by the memory.

7/18

ST24LC21