Symbol

Alt

Parameter

Min

Max

Unit

Clock Rise Time

1

µs

Clock Fall Time

300

ns

Input Rise Time

1

µs

Input Fall Time

300

ns

(1)

Clock High to Input Transition

4.7

µs

Clock Pulse Width High

4

µs

Input Low to Clock Low (START)

4

µs

Clock Low to Input Transition

0

µs

Clock Pulse Width Low

4.7

µs

Input Transition to Clock Transition

250

ns

Clock High to Input High (STOP)

4.7

µs

Input High to Input Low (Bus Free)

4.7

µs

(2)

Clock Low to Next Data Out Valid

0.3

3.5

µs

Data Out Hold Time

300

ns

Clock Frequency

100

kHz

Write Time

10

ms

Notes: 1. For a reSTART condition, or following a write cycle.

2. The minimum value delays the falling/rising edge of SDA away from SCL = 1 in order to avoid unwanted START and/or STOP

conditions.

Symbol

Alt

Parameter

Min

Max

Unit

Output Valid from VCLK

500

ns

VCLK High Time

600

ns

VCLK Low Time

1.3

µs

Mode Tansition Time

500

ns

(1,2)

Transmit-only Power-up Time

0

ns

(2)

VCLK Rise Time

1

µs

(2)

VCLK Fall Time

1

µs

Notes: 1. Refer to Figure 3.

2. Sampled only, not 100% tested.

Table 9. AC Characteristics, Transmit-only Mode

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ST24LC21