ST24LC21 datasheet(12/18 Pages) STMICROELECTRONICS

12 / 18 page

Read Operations

On delivery, the memory content is set at all "1’s"

(or FFh).

Current Address Read. The memory has an inter-

nal byte address counter. Each time a byte is read,

this counter is incremented. For the Current Ad-

dress Read mode, following a START condition,

the master sends a memory address with the RW

bit set to ’1’. The memory acknowledges this and

outputs the byte addressed by the internal byte

address counter. This counter is then incremented.

The master does NOT acknowledge the byte out-

put, but terminates the transfer with a STOP con-

dition.

Random Address Read. A dummy write is per-

formed to load the address into the address

counter, see Figure 12. This is followed by another

START condition from the master and the byte

address is repeated with the RW bit set to ’1’. The

memory acknowledges this and outputs the byte

addressed. The master does NOT acknowledge

the byte output, but terminates the transfer with a

STOP condition.

BYTE WRITE

DEV SEL

BYTE ADDR

DATA IN

PAGE WRITE

DEV SEL

BYTE ADDR

DATA IN 1

DATA IN 2

AI01504B

DATA IN N

ACK

R/W

ACK

R/W

ACK

VCLK

Figure 10. Write Modes Sequence

12/18

ST24LC21

ST24LC21 数据表(PDF) 12 Page - STMicroelectronics

ST24LC21 数据表(HTML) 12 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

数据表下载