ST24LC21 datasheet(5/18 Pages) STMICROELECTRONICS

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AI01665

VCC

CBUS

SDA

MASTER

SCL

CBUS

100

CBUS (pF)

1000

fc = 400kHz

fc = 100kHz

Figure 5. Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus

SIGNAL DESCRIPTIONS

I2C Serial Clock (SCL). The SCL input pin is used

to synchronize all data in and out of the memory. A

resistor can be connected from the SCL line to VCC

to act as a pull up (see Figure 5).

Transmit Only Clock (VCLK). The VCLK input pin

is used to synchronize data out when the

ST24LC21 is in Transmit Only mode. The VCLK

input offers also a Write Enable (active high) func-

tion when the ST24LC21 is in I2C bidirectional

mode.

Serial Data (SDA). The SDA pin is bi-directional

and is used to transfer data in or out of the memory.

It is an open drain output that may be wire-OR’ed

with other open drain or open collector signals on

the bus. A resistor must be connected from the SDA

bus line to VCC to act as pull up (see Figure 5).

DEVICE OPERATION

I2C Bus Background

The ST24LC21 supports the I2C protocol. This

protocol defines any device that sends data onto

the bus as a transmitter and any device that reads

the data as a receiver. The device that controls the

data transfer is known as the master and the other

as the slave. The master will always initiate a data

transfer and will provide the serial clock for syn-

chronisation. The ST24LC21 are always slave de-

vices in all communications.

Start Condition. START is identified by a high to

low transition of the SDA line while the clock SCL

is stable in the high state. A START condition must

precede any command for data transfer. Except

during a programming cycle, the ST24LC21 con-

tinuously monitor the SDA and SCL signals for a

START condition and will not respond unless one

is given.

Stop Condition. STOP is identified by a low to high

transition of the SDA line while the clock SCL is

stable in the high state. A STOP condition termi-

nates communication between the ST24LC21 and

the bus master. A STOP condition at the end of a

Read command forces the standby state. A STOP

condition at the end of a Write command triggers

the internal EEPROM write cycle.

Acknowledge Bit (ACK). An acknowledge signal

is used to indicate a successfull data transfer. The

bus transmitter, either master or slave, will release

the SDA bus after sending 8 bits of data. During the

9th clock pulse period the receiver pulls the SDA

bus low to acknowledge the receipt of the 8 bits of

data.

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ST24LC21

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