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AS1545 数据表(PDF) 9 Page - ams AG

部件名 AS1545
功能描述  Dual, 12-Bit, 1MSPS, SAR ADC
PDF  34 Pages
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制造商  AMSCO [ams AG]
网页  http://www.ams.com
标志 AMSCO - ams AG

AS1545 数据表(HTML) 9 Page - ams AG

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Revision 1.00
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AS1545
Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s
Timing Characteristics
AVDD = DVDD = 2.7V to 5.25V, VDRIVE = 2.7V to AVDD/DVDD, internal/external reference = 2.5V, TA = -40 to +85°C
(unless otherwise specified).
Figure 3. Timing Diagram
Table 4. Timing Characteristics
1
1. Based on simulation and characterised samples.
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Master Clock Frequency
fSCLK
120
MHz
Conversion Time
tCONVERT
tSCLK = 1/fSCLK
15 x
tSCLK
ns
fSCLK = 20 MHz
750
Quiet Time
tQUIET
Minimum time between end of serial
read and next falling edge of CSN
30
ns
CSN Fall to SCLK Fall Setup
Time
tCSS
VIL of CSN to VIL of SCLK
10
ns
CSN Fall to DOUT Enable
tCSDOE
VIL of CSN to Corner of DOUT
15
ns
SCLK Fall to DOUT Valid
2
2. VIL of SCLK to VOH of DOUT (rising edge) / VOL of DOUT (falling edge)
tDOV
VDD = 2.7V
40
ns
VDD = 5.25V
10
SCLK Fall to DOUT Hold
3
3. VIL of SCLK to VOL of DOUT (rising edge) / VOH of DOUT (falling edge)
tDOH
VDD = 2.7V
10
ns
VDD = 5.25V
5
SCLK Low Pulse Width
tCL
VIL to VIL of SCLK
0.4
tSCLK
0.6
tSCLK
SCLK High Pulse Width
tCH
VIH to VIH of SCLK
0.4
tSCLK
0.6
tSCLK
CSN Rise to DOUT Disable
tCSDOD
VIH of CSN to corner of DOUT to Tristate
20
ns
CSN Minimum Pulse Width
tCSPW
VIH to VIH of CSN
30
ns
SCLK Fall to DOUT Disable
tDOD
VIH of SCLK to corner of DOUT to
Tristate
550
ns
1
2
3
4
5
tCH
0
0
0DB11
DB10
DB9
DB2
DB1
DB0
THREE-STATE
3 LEADING ZEROES
THREE-
STATE
DOUTA
DOUTB
SCLK
CSN
tCSS
14
B
tCL
tCSDOD
tQUIET
tDOH
tDOV
tCSDOE
tCSPW



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