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AS1545

Data Sheet - A p p l i c a t i o n I n f o r m a t i o n

To enter partial power-down mode, the conversion process must be interrupted by bringing CSN high anywhere after

the second falling edge of SCLK and before the 10th falling edge of SCLK, as shown in Figure 50. Once CSN is

brought high in this window of SCLKs, the part enters partial power-down, the conversion that was initiated by the

second SCLK falling edge, the part remains in normal mode and does not power down. This avoids accidental power-

down due to glitches on the CSN line.

Figure 50. Partial Power-Down Mode

To exit this mode of operation and power up the AS1545 again, a dummy conversion is performed. On the falling edge

of CSN, the device begins to power up and continues to power up as long as CSN is held low until after the falling edge

of the 10th SCLK. The device is fully powered up after approximately 1 µs has elapsed, and valid data results from the

next conversion, as shown in Figure 47. If CSN is brought high before the second falling edge of SCLK, the AS1545

again goes into partial power-down. This avoids accidental power-up due to glitches on the CSN line. Although the

device may begin to power up on the falling edge of CSN, it powers down again on the rising edge of CSN. If the

AS1545 is already in partial power-down mode and CSN is brought high between the second and 10th falling edges of

SCLK, the device enters full power-down mode.

Power-Up Times

As described in detail, the AS1545 has two power-down modes, partial power-down and full power-down. This section

deals with the power-up time required when coming out of either of these modes. It should be noted that the power-up

The power-up time is always 1µs, independent of the mode currently in.

Note: It is important to note that, when using the internal reference, charging the external reference capacitance typ-

ically needs around 250µs but can take up to 1ms.

When power supplies are first applied to the AS1545, the ADC may power up in either of the power-down modes or

normal mode. Because of this, it is best to allow a dummy cycle to elapse to ensure the part is fully powered up before

attempting a valid conversion. Likewise, if it is intended to keep the part in the partial power-down mode immediately

after the supplies are applied, then two dummy cycles must be initiated. The first dummy cycle must hold CSN low until

after the 10th SCLK falling edge (see Figure 46); in the second cycle, CSN must be brought high before the 10th SCLK

edge but after the second SCLK falling edge (see Figure 50). Alternatively, if it is intended to place the part in full

power-down mode when the supplies are applied, then three dummy cycles must be initiated. The first dummy cycle

must hold CSN low until after the 10th SCLK falling edge (see Figure 46); the second and third dummy cycles place

the part in full power-down (see Figure 48).

Once supplies are applied to the AS1545, enough time must be allowed for any external reference to power up and

charge the various reference buffer decoupling capacitors to their final values.

1

15

10

SCLK

CSN

2

THREE-STATE