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AS1545

Data Sheet - A p p l i c a t i o n I n f o r m a t i o n

Power vs. Throughput Rate

The power consumption of the AS1545 varies with throughput rate. When using very slow throughput rates and as fast

an SCLK frequency as possible, the various power-down options can be used to make significant power savings.

However, the AS1545 quiescent current is low enough that even without using the power-down options, there is a

noticeable variation in power consumption with sampling rate. This is true whether a fixed SCLK value is used or if it is

scaled with the sampling rate. Figure 10 on page 11 shows plots of power vs. the throughput rate when operating in

normal mode for a fixed maximum SCLK frequency, and an SCLK frequency that scales with the sampling rate with

Serial Interface

The timing diagram for serial interfacing to the AS1545 is shown in Figure 51. The serial clock provides the conversion

clock and controls the transfer of information from the AS1545 during conversion.

The CSN signal initiates the data transfer and conversion process. The falling edge of CSN puts the track-and-hold

into hold mode, at which point the analog input is sampled and the bus is taken out of three-state. The conversion is

also initiated at this point and requires a minimum of 15 SCLKs to complete. Once 13 SCLK falling edges have

elapsed, the track-and-hold goes back into track on the next SCLK rising edge, as shown in Figure 51 at Point B. If a

16-SCLK transfer is used, then two trailing zeros will appear after the final LSB. On the rising edge of CSN, the

zero).

three-state on the 32nd SCLK falling edge or the rising edge of CSN, whichever occurs first.

A minimum of 15 serial clock cycles are required to perform the conversion process and to access data from one

conversion on either data line of the AS1545. CSN going low provides the 3 leading zeros to be read in by the

microcontroller or DSP. The remaining data is then clocked out by subsequent SCLK falling edges. Therefore, the first

falling clock edge on the serial clock has the leading zero provided and also clocks out the second leading zero. The

12-bit result then follows after a third leading zero with the final bit in the data transfer valid on the 15th falling edge,

having being clocked out on the previous (14th) falling edge. It may also be possible to read in data on each SCLK

rising edge depending on the SCLK frequency or the supply voltage. The secondrising edge of SCLK after the CSN

falling edge would have the third leading zero provided, and the 14th rising SCLK edge would have DB0 provided.

If a falling edge of SCLK is coincident with the falling edge of CSN, then this falling edge of SCLK is not acknowledged

by the AS1545, and the next falling edge of SCLK will be the first registered after the falling edge of CSN.

Figure 51. Timing Diagram

1

2

3

4

5

0

0

0DB11

DB10

DB9

DB2

DB1

DB0

THREE-STATE

3 LEADING ZEROES

THREE-

STATE

DOUTA

DOUTB

SCLK

CSN

14

B