T410 datasheet(8/84 Pages) STMICROELECTRONICS

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ST52T410/T420/E420

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When this phase starts, the ST52T410/ST52x420

core are set to RESET status; then 12V are applied

t o t h e V p p pi n i n o rder t o s t art E P R O M

programming. A signal applied to PB1 is used to

increm ent th e m emory address; the da ta i s

supplied to PORT A (see EPROM programming for

further details).

1.2.2 Working mode.

Below are the control signals of this mode:

The processor starts the working phase following

the instructions, which have been previously

loaded in the memory.

ST52T410/ST52x420’s internal structure includes

a computational block, CONTROL UNIT (CU) /

DATA PROCESSING UNIT (DPU), which allows

p roc essi ng of bo ol ea n fun ctio ns a nd fu zzy

algorithms.

The CU/DPU can manage up to 334 different

M e m bersh i p F unc ti ons fo r the f u zz y rul es

antecedent part. The rule consequents are “crisp”

values (real numbers). The maximum number of

rul es tha t can be defined i s l im ite d b y the

d i m e ns i o ns o f th e i m p l e m e n t ed s t an da rd

algorithm.

EPR OM i s th en sh are d be tw ee n fuzzy an d

standard algorithms. The Membership Function

data is stored inside the fi rst 1024 mem ory

locations. The Fuzzy rules are parts of the program

instructions.

The Control Unit (CU) reads the information and

the status deriving from the peripherals.

Arithmetic calculus can be performed on these

values by using the internal CU and the 128 bytes

of RAM, which supports all computations. The

peripheral input can be fuzzy and/or arithmetic

output, or the values contained in Data RAM and

EPROM locations.

Figure 1.1 ST52x420 SO28 Pin Configuration

RESET

TEST

VPP

VDD

VSS

RESET

OSCOUT

OSCIN

TEST

INT/PC0

T0OUT/PC1

T1OUT/PC2

T2OUT/PC3

Ain0/PB0

Ain1/PB1

Ain2/PB2

Ain3/PB3

VDDA

GNDA

VDD

VSS

VPP

PA0/T0RES

PA1/T0OUT

PA2/T1OUT

PA3/T2OUT

PA4/T0STRT

PA5/T0CLK

PA6

PA7/PB7/Ain7

PB6/Ain6

PB5/Ain5

PB4/Ain4

SO28

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