ST75951 datasheet(7/21 Pages) STMICROELECTRONICS

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% M

% Q

XTALIN

(MCLK)

XTALOUT

% R

MCM

% OVER

SCLK

Internal Sampling

Frequency

Sync

M/S

% 2

F0 or F0/2

% 2

GPIO1 or CL

GPIO2 or OH

Figure 2

4 - Power Down Mode

Two PowerDown modes are available in ST75951

thanks to bit 4 in control register 3.

4.1 - PowerDown Mode 0

If bit 4 is set to ’0’ then when PWRDWN is set to ’0’

the entire chip is in powerdown mode 0.

FUNCTIONAL DESCRIPTION (continued)

Normal

Power Down 0

Normal

PWRDWN

REG3 BIT4 = 0

Figure 3

4.2 - PowerDown Mode 1 (100

µW)

When bit 4 is set to ’1’ then when PWRDWN is set

to ’0’ the chip is in powerdown except the Ring detect

circuitry (wake-up on Ring = powerdown mode 1).

The general purpose interrupt is also working in

order to wake-up the system for dedicated cus-

tomer feature associated with a defined GPIO (pro-

grammed as input and non-masked).

4.2.1 - Ring Bit and GPIO Bit Masked

In this configuration the processor relies on the

Ring output pin to process the wake-up of the

system and does not need the SSI to be powered-

on. The SSI will be put back in operative mode

when PWRDWN is set to ’1’ (see Figure 4).

4.2.2 - Ring Bit or GPIO Bit Non-Masked

In this configuration the processor relies on the SSI

to process the wake-up of the system and needs

the SSI to be powered-on.

On an incoming Ring signal or an interrupt coming

thanks to the GPIO, ST75951 will generate an

interrupt on GPI output pin and power-up the SSI,

the processor will be able to read the control regis-

ter 2 and find out the origine of the interrupt.

After a reading of the register 2, if the processor

does not set high PWRDWN ST75951 puts back

the SSI off in order to save energy (see Figure 5).

ST75951

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