ST75951 datasheet(4/21 Pages) STMICROELECTRONICS

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PIN DESCRIPTION

1 - Power Supply (5 Pins)

1.1 - Power Supply (AVDD, DVDD)

These pins are the positive analog and digital

power supply input (2.7 to 5.25V).

In any case, the AVDD voltage must always be higher

or equal to the DVDD voltage (AVDD

≥ DVDD).

1.2 - Analog Ground ( AGND1, AGND2)

These pins are the ground return of the DAC and

ADC analog section.

1.3 - Digital ground (DGND)

This pin is the ground return of the digital circuitry.

Note : In order to obtain published performances,

the analog AVDD and digital DVDD should be decou-

pled with respect to analog ground and digital

ground, respectively. Decoupling capacitors should

be as close as possible to the supplies pins. All

ground must be tied together. In the following sec-

tion the ground is referred as : GND.

2 - Serial Synchronous Interface (4 Pins)

2.1 Data (DIN, DOUT)

Digital data word input/output of the SSI (16 bits

data).

2.2 - Frame Synchronization (FS)

The frame synchronization is used to indicate that

the device is ready to send and receive data.

The data transfer begins on the falling edge of

frame-sync signal. The frame-SYNC can be gener-

ated internally or externally.

2.3 Serial Bit Clock (SCLK)

Clocks the digital data into DIN and out of DOUT

during the frame synchronization interval. The se-

rial bit clock is generated internally and equal to

MCLK/R (R programmed value in register 3). The

serial bit clock is a multiple of FS.

3 - Control Pins (10 Pins)

3.1 - Reset (RESET)

This pin initializes the internal counters and control

registers to their default value. A minimum low

pulse of 100ns is required to reset the chip.

3.2 - Power-Down (PWRDWN)

This input powers down the entire chip. In power

down mode the existing internally programmed

state is maintained. When power down is driven

high, full operation resumes after 1ms.

A software powerdown with wake-up on ring detect

is also provided with bit 4 in control register 3.

3.3 - Hardware Control (HC0, HC1)

These pins are used for hardware/software control

programmation of the device.

3.4 - Hardware Control (HM)

This pin is used for hardware/software control of

CLID/OFFHOOK function.

3.5 - Master/Slave (M/S)

When M/S = " 1 " the device is in master mode and

FS is generated internally otherwise the device is

in slave mode and Fs must be provided externally

and equal to SCLK*R / OVER.

3.6 - Timeslot Control (TS)

When TS = " 0 " the data are assigned to the

first timeslot (1st 16 bits after falling edge of FS)

otherwise the data are on the second timeslot

(bits 17 to 32).

3.7 - Control (D5, D6)

These pins transmit the control signals trough iso-

lation capacitors to ST952 which converts and

outputs the appropriate control signals.

3.8 - Master Clock Mode (MCM)

When MCM = " 1 ", we have

FS = Master Clock/[M

⋅ Q ⋅ OVER] otherwise we

have FS = Master Clock/OVER and the M, Q

dividers are bypassed.

4 - General Purpose Input/Output Circuitry

4.1 - GPIO (4 Pins)

ST75951 offers 4 general purpose Input/Output

pins. The setting of the GPIO configuration is done

through the control register 1 and the signal level

of the GPIO are reflected in the feedback register 2.

At power on the GPIO are programmed as inputs.

In order to take into account the evolution of ST952,

thanks to the control register we will be able to send

a clock signal equal to F0/N (N programmed in

When in DAA control hardware mode HM = 1, the

CLID and OFF-HOOK control is done by Pin GPIO1

(CLID) and GPIO2 (OFF-HOOK), otherwise when

HM = 0 then the CLID/OFF-HOOK control is done

by programming the adequate bit in the control

ST75951

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