Table 7 : Control Register 3 : Clock / configuration setting

Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Function

0

1

1

OH CL

Software value (HM = 0)

0

1

1

0

Normal operation (INI)

0

1

1

1

PowerDown with wake-up

on ring or non-masked GPIO

0

1

1

0

Transmit modulated (INI)

0

1

1

1

Transmit not modulated

0

1

1

0

0

SCLK = MCLK (R = 1)

0

1

1

0

1

SCLK = MCLK/2 (R = 2) (INI)

0

1

1

1

0

SCLK = MCLK/4 (R = 4)

0

1

1

1

1

Reserved

0

1

1

0

0

Normal mode (INI)

0

1

1

0

1

Analog loop back

0

1

1

1

0

Digital loop back

0

1

1

1

1

Reserved

01100

Normal mode (INI)

01101

Reserved

01110

TSTD1 Pin = PCLK output

01111

TSTD1 Pin = PCLK input

Below you’ll find a table giving different programmation for achieving all common V.34 baud rate with

and the 16kHz for the 56K (V.pcm).

Table 8

Baud Rate

Over

M

Q

F0

16000

192

2

6

1536000

3429

13714.29

192

2

7

1316571

3000

12000

256

2

6

1536000

3490

10472.73

320

2

5.5

1675636

3429

10285.71

256

2

7

1316571

2400/3200

9600

320

2

6

1536000

3000

9000

256

2

8

1152000

2953

8861.54

320

2

6.5

1417846

2743

8228.57

320

2

7

1316571

8000

384

2

6

1536000

2400

7200

320

2

8

1152000

In any cases attention must be paid to have F0 between 1MHz and 1.7 MHz , optimum value beeing 1.5MHz.

The modulator and demodulator frequency F0 = OVERSAMPLING FREQUENCY / 2.

When MCM = ’ 0’, we have OVERSAMPLING FREQUENCY = MCLK and F0 = MCLK / 2 SCLK = MCLK / R

(see clock block diagram).

Table 9 : (eg : with R = 4)

M

Q

Over

MCLK (MHz)

F0 (MKz)

SCLK (kHz)

8

X

X

384

3.072

1.536

768

9.6

X

X

320

3.072

1.536

768

9.6

X

X

256

2.4576

1.2288

614.4

16

X

X

192

3.072

1.536

768

FUNCTIONAL DESCRIPTION (continued)

ST75951

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