ST7LITE05 datasheet(83/122 Pages) STMICROELECTRONICS

83 / 122 page

ST7LITE0, ST7SUPERLITE

83/122

OPERATING CONDITIONS (Cont’d)

13.3.4.2 Devices with ‘”6” order code suffix (tested for TA = -40 to +85°C) @ VDD = 2.7 to 3.3V

Notes:

1. Data based on characterization results, not tested in production

2. RCCR1 is a factory-calibrated setting for 700kHz with ±2% accuracy @ TA =25°C, VDD=3V. See “INTERNAL RC OS-

CILLATOR ADJUSTMENT” on page 23.

3. Guaranteed by design.

4. Averaged over a 4ms period. After the LOCKED bit is set, a period of tSTAB is required to reach ACCPLL accuracy

5. After the LOCKED bit is set ACCPLL is max. 10% until tSTAB has elapsed. See Figure 12 on page 24.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fRC

Internal RC oscillator fre-

quency

RCCR = FF (reset value), TA=25°C, VDD= 3.0V

560

kHz

RCCR=RCCR12) ,TA=25°C,VDD= 3V

700

ACCRC

Accuracy of Internal RC

oscillator when calibrated

with RCCR=RCCR11)2)

TA=25°C,VDD=3V

-2

TA=25°C,VDD=2.7 to 3.3V

-25

+25

TA=-40 to +85°C,VDD=3V

-15

IDD(RC)

RC oscillator current con-

sumption

TA=25°C,VDD=3V

7001)

µA

tsu(RC)

RC oscillator setup time

TA=25°C,VDD=3V

102)

µs

fPLL

x4 PLL input clock

11)

MHz

tLOCK

PLL Lock time5)

2ms

tSTAB

PLL Stabilization time5)

4ms

ACCPLL

x4 PLL Accuracy

fRC = 1MHz@TA=25°C,VDD=2.7 to 3.3V

0.14)

fRC = 1MHz@TA=40 to +85°C,VDD= 3V

0.14)

tw(JIT)

PLL jitter period

fRC = 1MHz

83)

kHz

JITPLL

PLL jitter (

∆f

CPU/fCPU)1

IDD(PLL)

PLL current consumption TA=25°C

1901)

µA

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